[llvm] [llvm][AArch64][Assembly]: Add FP8FMA assembly and disassembly. (PR #70134)
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Tue Oct 24 15:26:20 PDT 2023
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git-clang-format --diff a3c68754b089872ac6d5349cf24439a90835d196 073e9dbebab03808983548257ccd232c64a5dd35 -- llvm/include/llvm/TargetParser/AArch64TargetParser.h llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp llvm/unittests/TargetParser/TargetParserTest.cpp
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diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index e6129c764186..1a730a0b955d 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -982,7 +982,7 @@ unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
case AArch64::FPR16_loRegClassID:
return 16;
case AArch64::FPR128_0to7RegClassID:
- return 8;
+ return 8;
}
}
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 62c6ecf196e5..71cc419bc800 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1226,7 +1226,7 @@ public:
bool isNeonVectorReg0to7() const {
return Kind == k_Register && Reg.Kind == RegKind::NeonVector &&
(AArch64MCRegisterClasses[AArch64::FPR128_0to7RegClassID].contains(
- Reg.RegNum));
+ Reg.RegNum));
}
bool isMatrix() const { return Kind == k_MatrixRegister; }
@@ -2609,27 +2609,26 @@ static std::optional<std::pair<int, int>> parseVectorKind(StringRef Suffix,
switch (VectorKind) {
case RegKind::NeonVector:
- Res =
- StringSwitch<std::pair<int, int>>(Suffix.lower())
- .Case("", {0, 0})
- .Case(".1d", {1, 64})
- .Case(".1q", {1, 128})
- .Case(".2b", {2, 8})
- .Case(".2s", {2, 32})
- .Case(".2d", {2, 64})
- .Case(".4h", {4, 16})
- .Case(".4s", {4, 32})
- .Case(".8b", {8, 8})
- .Case(".8h", {8, 16})
- .Case(".16b", {16, 8})
- // Accept the width neutral ones, too, for verbose syntax. If those
- // aren't used in the right places, the token operand won't match so
- // all will work out.
- .Case(".b", {0, 8})
- .Case(".h", {0, 16})
- .Case(".s", {0, 32})
- .Case(".d", {0, 64})
- .Default({-1, -1});
+ Res = StringSwitch<std::pair<int, int>>(Suffix.lower())
+ .Case("", {0, 0})
+ .Case(".1d", {1, 64})
+ .Case(".1q", {1, 128})
+ .Case(".2b", {2, 8})
+ .Case(".2s", {2, 32})
+ .Case(".2d", {2, 64})
+ .Case(".4h", {4, 16})
+ .Case(".4s", {4, 32})
+ .Case(".8b", {8, 8})
+ .Case(".8h", {8, 16})
+ .Case(".16b", {16, 8})
+ // Accept the width neutral ones, too, for verbose syntax. If
+ // those aren't used in the right places, the token operand won't
+ // match so all will work out.
+ .Case(".b", {0, 8})
+ .Case(".h", {0, 16})
+ .Case(".s", {0, 32})
+ .Case(".d", {0, 64})
+ .Default({-1, -1});
break;
case RegKind::SVEPredicateAsCounter:
case RegKind::SVEPredicateVector:
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index d943b8fe88f4..cf2d3879292d 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -44,9 +44,9 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder);
-static DecodeStatus DecodeFPR128_0to7RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
+static DecodeStatus
+DecodeFPR128_0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
+ const MCDisassembler *Decoder);
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder);
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 4b21290f1677..732c68190bb3 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1713,25 +1713,25 @@ TEST(TargetParserTest, testAArch64Extension) {
TEST(TargetParserTest, AArch64ExtensionFeatures) {
std::vector<uint64_t> Extensions = {
- AArch64::AEK_CRC, AArch64::AEK_LSE, AArch64::AEK_RDM,
- AArch64::AEK_CRYPTO, AArch64::AEK_SM4, AArch64::AEK_SHA3,
- AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_DOTPROD,
- AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_FP16,
- AArch64::AEK_FP16FML, AArch64::AEK_PROFILE, AArch64::AEK_RAS,
- AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SVE2AES,
- AArch64::AEK_SVE2SM4, AArch64::AEK_SVE2SHA3, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_RCPC, AArch64::AEK_RAND, AArch64::AEK_MTE,
- AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_PREDRES,
- AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_F32MM,
- AArch64::AEK_F64MM, AArch64::AEK_TME, AArch64::AEK_LS64,
- AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
- AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
- AArch64::AEK_SME2, AArch64::AEK_HBC, AArch64::AEK_MOPS,
- AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1, AArch64::AEK_SME2p1,
- AArch64::AEK_B16B16, AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
- AArch64::AEK_RCPC3, AArch64::AEK_THE, AArch64::AEK_D128,
- AArch64::AEK_LSE128, AArch64::AEK_SPECRES2, AArch64::AEK_RASv2,
- AArch64::AEK_ITE, AArch64::AEK_GCS, AArch64::AEK_FPMR,
+ AArch64::AEK_CRC, AArch64::AEK_LSE, AArch64::AEK_RDM,
+ AArch64::AEK_CRYPTO, AArch64::AEK_SM4, AArch64::AEK_SHA3,
+ AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_DOTPROD,
+ AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_FP16,
+ AArch64::AEK_FP16FML, AArch64::AEK_PROFILE, AArch64::AEK_RAS,
+ AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SVE2AES,
+ AArch64::AEK_SVE2SM4, AArch64::AEK_SVE2SHA3, AArch64::AEK_SVE2BITPERM,
+ AArch64::AEK_RCPC, AArch64::AEK_RAND, AArch64::AEK_MTE,
+ AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_PREDRES,
+ AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_F32MM,
+ AArch64::AEK_F64MM, AArch64::AEK_TME, AArch64::AEK_LS64,
+ AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
+ AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
+ AArch64::AEK_SME2, AArch64::AEK_HBC, AArch64::AEK_MOPS,
+ AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1, AArch64::AEK_SME2p1,
+ AArch64::AEK_B16B16, AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
+ AArch64::AEK_RCPC3, AArch64::AEK_THE, AArch64::AEK_D128,
+ AArch64::AEK_LSE128, AArch64::AEK_SPECRES2, AArch64::AEK_RASv2,
+ AArch64::AEK_ITE, AArch64::AEK_GCS, AArch64::AEK_FPMR,
AArch64::AEK_FP8FMA, AArch64::AEK_SSVE_FP8FMA};
std::vector<StringRef> Features;
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https://github.com/llvm/llvm-project/pull/70134
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