[llvm] [AMDGPU] Set Write64Bit = Write64Bit on V_MOV_B64 (PR #70135)

[Stanislav Mekhanoshin via llvm-commits]

https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/70135

This is mostly NFCI as V_MOV_B64_PSEUDO is selected instead and expanded past RA.

>From 7a451f273ce511dc38cb0f5539e44d5733f3cc04 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: Tue, 24 Oct 2023 15:03:00 -0700
Subject: [PATCH] [AMDGPU] Set Write64Bit = Write64Bit on V_MOV_B64

This is mostly NFCI as V_MOV_B64_PSEUDO is selected instead and
expanded past RA.
---
 llvm/lib/Target/AMDGPU/VOP1Instructions.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 734db326fb77ddd..9c19091e3d583f1 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -221,7 +221,7 @@ def VOPProfile_MOV : VOPProfile <[i32, i32, untyped, untyped]> {
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 defm V_MOV_B32 : VOP1Inst <"v_mov_b32", VOPProfile_MOV, null_frag, 0x8>;
 
-let SubtargetPredicate = isGFX940Plus in
+let SubtargetPredicate = isGFX940Plus, SchedRW = [Write64Bit] in
 defm V_MOV_B64 : VOP1Inst <"v_mov_b64", VOP_I64_I64>;
 } // End isMoveImm = 1