[llvm] [RISCV][GISel] Falling back to SDISel for scalable vector type values (PR #70133)
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 24 15:12:23 PDT 2023
https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/70133
This patch also tests the fallback of unsupported formal arguments.
>From 8404468f4eae830335054d2aebf3d5bab0f4e84f Mon Sep 17 00:00:00 2001
From: Min Hsu <min.hsu at sifive.com>
Date: Tue, 24 Oct 2023 15:00:16 -0700
Subject: [PATCH] [RISCV][GISel] Falling back to SDISel for scalable vector
type values
This patch also tests the fallback of unsupported formal arguments.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 17 +++++++
llvm/lib/Target/RISCV/RISCVISelLowering.h | 2 +
.../RISCV/GlobalISel/irtranslator/fallback.ll | 44 +++++++++++++++++++
3 files changed, 63 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1f56ca17b785bc0..69abcd561acd1ea 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -19304,6 +19304,23 @@ unsigned RISCVTargetLowering::getCustomCtpopCost(EVT VT,
return isCtpopFast(VT) ? 0 : 1;
}
+bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
+ // We don't support scalable vectors in GISel.
+ if (Inst.getType()->isScalableTy())
+ return true;
+
+ for (unsigned i = 0; i < Inst.getNumOperands(); ++i)
+ if (Inst.getOperand(i)->getType()->isScalableTy())
+ return true;
+
+ if (const AllocaInst *AI = dyn_cast<AllocaInst>(&Inst)) {
+ if (AI->getAllocatedType()->isScalableTy())
+ return true;
+ }
+
+ return false;
+}
+
namespace llvm::RISCVVIntrinsicsTable {
#define GET_RISCVVIntrinsicsTable_IMPL
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 2675b0ce43e439f..e13b92be6dbdd91 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -800,6 +800,8 @@ class RISCVTargetLowering : public TargetLowering {
unsigned getMaxSupportedInterleaveFactor() const override { return 8; }
+ bool fallBackToDAGISel(const Instruction &Inst) const override;
+
bool lowerInterleavedLoad(LoadInst *LI,
ArrayRef<ShuffleVectorInst *> Shuffles,
ArrayRef<unsigned> Indices,
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll
new file mode 100644
index 000000000000000..5dd62de8a6bc415
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll
@@ -0,0 +1,44 @@
+; RUN: llc -mtriple=riscv64 -mattr='+v' -O0 -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o %t.out 2> %t.err
+; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out
+; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err
+
+
+declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
+ <vscale x 1 x i8>,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i8>,
+ i64)
+
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to lower arguments{{.*}}scalable_arg
+; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_arg
+define <vscale x 1 x i8> @scalable_arg(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+entry:
+ %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
+ <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> %0,
+ <vscale x 1 x i8> %1,
+ i64 %2)
+
+ ret <vscale x 1 x i8> %a
+}
+
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction{{.*}}scalable_inst
+; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_inst
+define <vscale x 1 x i8> @scalable_inst(i64 %0) nounwind {
+entry:
+ %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
+ <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> undef,
+ i64 %0)
+
+ ret <vscale x 1 x i8> %a
+}
+
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction{{.*}}scalable_alloca
+; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_alloca
+define void @scalable_alloca() #1 {
+ %local0 = alloca <vscale x 16 x i8>
+ load volatile <vscale x 16 x i8>, ptr %local0
+ ret void
+}
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