[llvm] 20020c1 - [DAGCombiner] Fix misuse of getZeroExtendInReg in SimplifySelectCC. (#70066)

[via llvm-commits]

Author: Craig Topper
Date: 2023-10-24T12:35:55-07:00
New Revision: 20020c1b43d543034dcc4a0c1715db558d6de773

URL: https://github.com/llvm/llvm-project/commit/20020c1b43d543034dcc4a0c1715db558d6de773
DIFF: https://github.com/llvm/llvm-project/commit/20020c1b43d543034dcc4a0c1715db558d6de773.diff

LOG: [DAGCombiner] Fix misuse of getZeroExtendInReg in SimplifySelectCC. (#70066)

If VT has less bits than SCC, using a ZeroExtendInReg isn't going to fix
it. That's an AND instruction. We need to truncate the value instead.

This should be ok because we already checked that the boolean contents
is ZeroOrOne so the setcc can only produce 0 or 1.

No test because I found this while trying to make i32 legal for RISC-V
64 which I'm not ready to upload yet. You can see in the coverage report
that this line isn't tested today.


https://lab.llvm.org/coverage/coverage-reports/coverage/Users/buildslave/jenkins/workspace/coverage/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp.html#L27270

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index c0a737b70c460e7..ca5bd4952866886 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -27274,10 +27274,7 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
     // zext (setcc n0, n1)
     if (LegalTypes) {
       SCC = DAG.getSetCC(DL, CmpResVT, N0, N1, CC);
-      if (VT.bitsLT(SCC.getValueType()))
-        Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2), VT);
-      else
-        Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), VT, SCC);
+      Temp = DAG.getZExtOrTrunc(SCC, SDLoc(N2), VT);
     } else {
       SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
       Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), VT, SCC);