[llvm] [DAGCombiner] Fix misuse of getZeroExtendInReg in SimplifySelectCC. (PR #70066)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/70066

If VT has less bits than SCC, using a ZeroExtendInReg isn't going to fix it. That's an AND instruction. We need to truncate the value instead.

This should be ok because we already checked that the boolean contents is ZeroOrOne so the setcc can only produce 0 or 1.

No test because I found this while trying to make i32 legal for RISC-V 64 which I'm not ready to upload yet. You can see in the coverage report that this line isn't tested today.

https://lab.llvm.org/coverage/coverage-reports/coverage/Users/buildslave/jenkins/workspace/coverage/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp.html#L27270

>From f9f5f802da34ae75409cdefec359e50cf4514f8e Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 24 Oct 2023 10:20:25 -0700
Subject: [PATCH] [DAGCombiner] Fix misuse of getZeroExtendInReg in
 SimplifySelectCC.

If VT has less bits than SCC, using a ZeroExtendInReg isn't going
to fix it. That's an AND instruction. We need to truncate the value
instead.

This should be ok because we already checked that the boolean
contents is ZeroOrOne so the setcc can only produce 0 or 1.

No test because I found this while trying to make i32 legal for
RISC-V 64 which I'm not ready to upload yet. You can see in the
coverage report that this line isn't tested today.

https://lab.llvm.org/coverage/coverage-reports/coverage/Users/buildslave/jenkins/workspace/coverage/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp.html#L27270
---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index c0a737b70c460e7..ca5bd4952866886 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -27274,10 +27274,7 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
     // zext (setcc n0, n1)
     if (LegalTypes) {
       SCC = DAG.getSetCC(DL, CmpResVT, N0, N1, CC);
-      if (VT.bitsLT(SCC.getValueType()))
-        Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2), VT);
-      else
-        Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), VT, SCC);
+      Temp = DAG.getZExtOrTrunc(SCC, SDLoc(N2), VT);
     } else {
       SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
       Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), VT, SCC);