[llvm] 9f592cb - [GISel] Pass MPO and VA to assignValueToAddress by const reference. NFC (#69810)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 24 09:58:27 PDT 2023
Author: Craig Topper
Date: 2023-10-24T09:58:22-07:00
New Revision: 9f592cbc18e13c918fe125c26ca881d303e0ff3d
URL: https://github.com/llvm/llvm-project/commit/9f592cbc18e13c918fe125c26ca881d303e0ff3d
DIFF: https://github.com/llvm/llvm-project/commit/9f592cbc18e13c918fe125c26ca881d303e0ff3d.diff
LOG: [GISel] Pass MPO and VA to assignValueToAddress by const reference. NFC (#69810)
Previously they were passed by non-const reference. No in tree target
modifies the values.
This makes it possible to call assignValueToAddress from
assignCustomValue without a const_cast. For example in this patch
https://github.com/llvm/llvm-project/pull/69138.
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
llvm/lib/Target/ARM/ARMCallLowering.cpp
llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp
llvm/lib/Target/M68k/GISel/M68kCallLowering.h
llvm/lib/Target/Mips/MipsCallLowering.cpp
llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h
llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
llvm/lib/Target/X86/GISel/X86CallLowering.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
index 4a799eec8899a51..6fbcb744e624a81 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
@@ -274,16 +274,16 @@ class CallLowering {
/// location. Load or store it there, with appropriate extension
/// if necessary.
virtual void assignValueToAddress(Register ValVReg, Register Addr,
- LLT MemTy, MachinePointerInfo &MPO,
- CCValAssign &VA) = 0;
+ LLT MemTy, const MachinePointerInfo &MPO,
+ const CCValAssign &VA) = 0;
/// An overload which takes an ArgInfo if additional information about the
/// arg is needed. \p ValRegIndex is the index in \p Arg.Regs for the value
/// to store.
virtual void assignValueToAddress(const ArgInfo &Arg, unsigned ValRegIndex,
Register Addr, LLT MemTy,
- MachinePointerInfo &MPO,
- CCValAssign &VA) {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) {
assignValueToAddress(Arg.Regs[ValRegIndex], Addr, MemTy, MPO, VA);
}
@@ -311,7 +311,7 @@ class CallLowering {
/// Extend a register to the location type given in VA, capped at extending
/// to at most MaxSize bits. If MaxSizeBits is 0 then no maximum is set.
- Register extendRegister(Register ValReg, CCValAssign &VA,
+ Register extendRegister(Register ValReg, const CCValAssign &VA,
unsigned MaxSizeBits = 0);
};
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index f4bee2a539b246c..78f019cff5b2f30 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -1135,7 +1135,7 @@ void CallLowering::ValueHandler::copyArgumentMemory(
}
Register CallLowering::ValueHandler::extendRegister(Register ValReg,
- CCValAssign &VA,
+ const CCValAssign &VA,
unsigned MaxSizeBits) {
LLT LocTy{VA.getLocVT()};
LLT ValTy{VA.getValVT()};
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index 1c5d1e904b87a0d..02c1ad49c0004ce 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -164,7 +164,8 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
}
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
LLT ValTy(VA.getValVT());
@@ -290,7 +291,8 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
}
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
inferAlignFromPtrInfo(MF, MPO));
@@ -298,8 +300,9 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
}
void assignValueToAddress(const CallLowering::ArgInfo &Arg, unsigned RegIndex,
- Register Addr, LLT MemTy, MachinePointerInfo &MPO,
- CCValAssign &VA) override {
+ Register Addr, LLT MemTy,
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override {
unsigned MaxSize = MemTy.getSizeInBytes() * 8;
// For varargs, we always want to extend them to 8 bytes, in which case
// we disable setting a max.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index db0f56416051f01..08bce3b2fc69244 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -32,7 +32,7 @@ namespace {
/// Wrapper around extendRegister to ensure we extend to a full 32-bit register.
static Register extendRegisterMin32(CallLowering::ValueHandler &Handler,
- Register ValVReg, CCValAssign &VA) {
+ Register ValVReg, const CCValAssign &VA) {
if (VA.getLocVT().getSizeInBits() < 32) {
// 16-bit types are reported as legal for 32-bit registers. We need to
// extend and do a 32-bit copy to avoid the verifier complaining about it.
@@ -56,7 +56,8 @@ struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
}
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override {
llvm_unreachable("not implemented");
}
@@ -137,7 +138,8 @@ struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler {
}
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
auto MMO = MF.getMachineMemOperand(
@@ -236,7 +238,8 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
}
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
uint64_t LocMemOffset = VA.getLocMemOffset();
const auto &ST = MF.getSubtarget<GCNSubtarget>();
@@ -249,7 +252,8 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
void assignValueToAddress(const CallLowering::ArgInfo &Arg,
unsigned ValRegIndex, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override {
Register ValVReg = VA.getLocInfo() != CCValAssign::LocInfo::FPExt
? extendRegister(Arg.Regs[ValRegIndex], VA)
: Arg.Regs[ValRegIndex];
diff --git a/llvm/lib/Target/ARM/ARMCallLowering.cpp b/llvm/lib/Target/ARM/ARMCallLowering.cpp
index 0383145afdb06f3..d1987e32f0e0bef 100644
--- a/llvm/lib/Target/ARM/ARMCallLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMCallLowering.cpp
@@ -123,7 +123,8 @@ struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
}
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override {
Register ExtReg = extendRegister(ValVReg, VA);
auto MMO = MIRBuilder.getMF().getMachineMemOperand(
MPO, MachineMemOperand::MOStore, MemTy, Align(1));
@@ -255,7 +256,8 @@ struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler {
}
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override {
if (VA.getLocInfo() == CCValAssign::SExt ||
VA.getLocInfo() == CCValAssign::ZExt) {
// If the value is zero- or sign-extended, its size becomes 4 bytes, so
@@ -272,7 +274,7 @@ struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler {
}
MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO) {
+ const MachinePointerInfo &MPO) {
MachineFunction &MF = MIRBuilder.getMF();
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
diff --git a/llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp b/llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp
index b0ada29d1ceab24..feeee198b1d891f 100644
--- a/llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp
+++ b/llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp
@@ -43,7 +43,8 @@ struct M68kOutgoingArgHandler : public CallLowering::OutgoingValueHandler {
}
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
Register ExtReg = extendRegister(ValVReg, VA);
@@ -132,11 +133,9 @@ void M68kIncomingValueHandler::assignValueToReg(Register ValVReg,
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
}
-void M68kIncomingValueHandler::assignValueToAddress(Register ValVReg,
- Register Addr,
- LLT MemTy,
- MachinePointerInfo &MPO,
- CCValAssign &VA) {
+void M68kIncomingValueHandler::assignValueToAddress(
+ Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
+ const CCValAssign &VA) {
MachineFunction &MF = MIRBuilder.getMF();
auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
inferAlignFromPtrInfo(MF, MPO));
diff --git a/llvm/lib/Target/M68k/GISel/M68kCallLowering.h b/llvm/lib/Target/M68k/GISel/M68kCallLowering.h
index a1589e96aa3d9ce..9fde508c188457b 100644
--- a/llvm/lib/Target/M68k/GISel/M68kCallLowering.h
+++ b/llvm/lib/Target/M68k/GISel/M68kCallLowering.h
@@ -56,7 +56,8 @@ struct M68kIncomingValueHandler : public CallLowering::IncomingValueHandler {
CCValAssign VA) override;
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override;
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override;
Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO,
diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp
index 4d6ca5ac2bcc6b3..2c276ffa4aebbc2 100644
--- a/llvm/lib/Target/Mips/MipsCallLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp
@@ -99,7 +99,8 @@ class MipsIncomingValueHandler : public CallLowering::IncomingValueHandler {
MachinePointerInfo &MPO,
ISD::ArgFlagsTy Flags) override;
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override;
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override;
unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
ArrayRef<CCValAssign> VAs,
@@ -149,10 +150,9 @@ Register MipsIncomingValueHandler::getStackAddress(uint64_t Size,
return MIRBuilder.buildFrameIndex(LLT::pointer(0, 32), FI).getReg(0);
}
-void MipsIncomingValueHandler::assignValueToAddress(Register ValVReg,
- Register Addr, LLT MemTy,
- MachinePointerInfo &MPO,
- CCValAssign &VA) {
+void MipsIncomingValueHandler::assignValueToAddress(
+ Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
+ const CCValAssign &VA) {
MachineFunction &MF = MIRBuilder.getMF();
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
inferAlignFromPtrInfo(MF, MPO));
@@ -207,7 +207,8 @@ class MipsOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
ISD::ArgFlagsTy Flags) override;
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override;
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override;
unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
ArrayRef<CCValAssign> VAs,
std::function<void()> *Thunk) override;
@@ -240,10 +241,9 @@ Register MipsOutgoingValueHandler::getStackAddress(uint64_t Size,
return AddrReg.getReg(0);
}
-void MipsOutgoingValueHandler::assignValueToAddress(Register ValVReg,
- Register Addr, LLT MemTy,
- MachinePointerInfo &MPO,
- CCValAssign &VA) {
+void MipsOutgoingValueHandler::assignValueToAddress(
+ Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
+ const CCValAssign &VA) {
MachineFunction &MF = MIRBuilder.getMF();
uint64_t LocMemOffset = VA.getLocMemOffset();
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp b/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
index 3913ede3dc186e7..2730ee32430df2f 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
@@ -38,7 +38,8 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override;
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override;
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override;
Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO,
ISD::ArgFlagsTy Flags) override;
@@ -56,8 +57,8 @@ void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg,
void OutgoingArgHandler::assignValueToAddress(Register ValVReg, Register Addr,
LLT MemTy,
- MachinePointerInfo &MPO,
- CCValAssign &VA) {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) {
llvm_unreachable("unimplemented");
}
@@ -148,13 +149,13 @@ void PPCIncomingValueHandler::assignValueToReg(Register ValVReg,
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
}
-void PPCIncomingValueHandler::assignValueToAddress(Register ValVReg,
- Register Addr, LLT MemTy,
- MachinePointerInfo &MPO,
- CCValAssign &VA) {
+void PPCIncomingValueHandler::assignValueToAddress(
+ Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
+ const CCValAssign &VA) {
// define a lambda expression to load value
- auto BuildLoad = [](MachineIRBuilder &MIRBuilder, MachinePointerInfo &MPO,
- LLT MemTy, const DstOp &Res, Register Addr) {
+ auto BuildLoad = [](MachineIRBuilder &MIRBuilder,
+ const MachinePointerInfo &MPO, LLT MemTy,
+ const DstOp &Res, Register Addr) {
MachineFunction &MF = MIRBuilder.getMF();
auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
inferAlignFromPtrInfo(MF, MPO));
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h b/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h
index cc2cb7b26e844b0..43152305ff7e0a2 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h
+++ b/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h
@@ -49,7 +49,8 @@ class PPCIncomingValueHandler : public CallLowering::IncomingValueHandler {
CCValAssign VA) override;
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override;
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override;
Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO,
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
index b605f2f621d040d..ec3825a6f780e62 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -78,7 +78,8 @@ struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
}
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
uint64_t LocMemOffset = VA.getLocMemOffset();
@@ -155,7 +156,8 @@ struct RISCVIncomingValueHandler : public CallLowering::IncomingValueHandler {
}
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
inferAlignFromPtrInfo(MF, MPO));
diff --git a/llvm/lib/Target/X86/GISel/X86CallLowering.cpp b/llvm/lib/Target/X86/GISel/X86CallLowering.cpp
index a47a09414cf76d2..d1e28a071c99594 100644
--- a/llvm/lib/Target/X86/GISel/X86CallLowering.cpp
+++ b/llvm/lib/Target/X86/GISel/X86CallLowering.cpp
@@ -113,7 +113,8 @@ struct X86OutgoingValueHandler : public CallLowering::OutgoingValueHandler {
}
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
Register ExtReg = extendRegister(ValVReg, VA);
@@ -201,7 +202,8 @@ struct X86IncomingValueHandler : public CallLowering::IncomingValueHandler {
}
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
- MachinePointerInfo &MPO, CCValAssign &VA) override {
+ const MachinePointerInfo &MPO,
+ const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
auto *MMO = MF.getMachineMemOperand(
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, MemTy,
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