[llvm] [AMDGPU] Add documentation for scheduler intrinsics (PR #69854)

[Jeffrey Byrnes via llvm-commits]

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@@ -1098,6 +1098,53 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
                                                    with the fifth i32 operand. The i1 sixth operand is used to clamp
                                                    the output. The i1s preceding the vector operands decide the signedness.
 
+  llvm.amdgcn.sched_barrier                        Controls the types of instructions that may be allowed to cross the intrinsic
+                                                   during instruction scheduling. The parameter is a mask for the instruction types
+                                                   that can cross the intrinsic.
+
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jrbyrnes wrote:

Perhaps a note that the mask is additive (and not negatable)? E.g. 0x0006 Allows VALU or SALU. 0x03FC allows everything but VALU. But ~(0x0002) is an error. 

Similar for sched_group_barrier, 0x0006 creates schedgroup which can contain either VALU or SALU

https://github.com/llvm/llvm-project/pull/69854