[llvm] [AArch64][GlobalISel] Legalize NEON smin,smax,umin,umax,fmin,fmax intrinsics (PR #70060)
Vladislav Dzhidzhoev via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 24 09:21:56 PDT 2023
https://github.com/dzhidzhoev created https://github.com/llvm/llvm-project/pull/70060
Replace these intrinsics with the corresponding GISel operators during
legalization stage to reuse available selection patterns.
>From eef0c8c43d9fb15b97ab0097f5021ff06eb6ecde Mon Sep 17 00:00:00 2001
From: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Date: Tue, 24 Oct 2023 18:14:55 +0200
Subject: [PATCH] [AArch64][GlobalISel] Legalize NEON
smin,smax,umin,umax,fmin,fmax intrinsics
Replace these intrinsics with the corresponding GISel operators during
legalization stage to reuse available selection patterns.
---
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 24 +++++++++++++++++++
llvm/test/CodeGen/AArch64/arm64-vmax.ll | 1 +
2 files changed, 25 insertions(+)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index ddc27bebb767693..780f6168d6011cb 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1284,6 +1284,30 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
return true;
}
+ case Intrinsic::aarch64_neon_smax:
+ case Intrinsic::aarch64_neon_smin:
+ case Intrinsic::aarch64_neon_umax:
+ case Intrinsic::aarch64_neon_umin:
+ case Intrinsic::aarch64_neon_fmax:
+ case Intrinsic::aarch64_neon_fmin: {
+ MachineIRBuilder MIB(MI);
+ if (IntrinsicID == Intrinsic::aarch64_neon_smax)
+ MIB.buildSMax(MI.getOperand(0), MI.getOperand(2), MI.getOperand(3));
+ else if (IntrinsicID == Intrinsic::aarch64_neon_smin)
+ MIB.buildSMin(MI.getOperand(0), MI.getOperand(2), MI.getOperand(3));
+ else if (IntrinsicID == Intrinsic::aarch64_neon_umax)
+ MIB.buildUMax(MI.getOperand(0), MI.getOperand(2), MI.getOperand(3));
+ else if (IntrinsicID == Intrinsic::aarch64_neon_umin)
+ MIB.buildUMin(MI.getOperand(0), MI.getOperand(2), MI.getOperand(3));
+ else if (IntrinsicID == Intrinsic::aarch64_neon_fmax)
+ MIB.buildInstr(TargetOpcode::G_FMAXIMUM, {DstOp(MI.getOperand(0))},
+ {SrcOp(MI.getOperand(2)), SrcOp(MI.getOperand(3))});
+ else if (IntrinsicID == Intrinsic::aarch64_neon_fmin)
+ MIB.buildInstr(TargetOpcode::G_FMINIMUM, {DstOp(MI.getOperand(0))},
+ {SrcOp(MI.getOperand(2)), SrcOp(MI.getOperand(3))});
+ MI.eraseFromParent();
+ return true;
+ }
case Intrinsic::experimental_vector_reverse:
// TODO: Add support for vector_reverse
return false;
diff --git a/llvm/test/CodeGen/AArch64/arm64-vmax.ll b/llvm/test/CodeGen/AArch64/arm64-vmax.ll
index de24544f9270bc1..d0a36b76cc61a19 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vmax.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vmax.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -global-isel -global-isel-abort=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @smax_8b(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: smax_8b:
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