[llvm] [SimplifyCFG] Delete the unnecessary range check for small mask operation (PR #65835)
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llvm-commits at lists.llvm.org
Tue Oct 24 06:39:41 PDT 2023
https://github.com/vfdff updated https://github.com/llvm/llvm-project/pull/65835
>From d312351f98b8735a26b7077713d59a6f255ee280 Mon Sep 17 00:00:00 2001
From: zhongyunde 00443407 <zhongyunde at huawei.com>
Date: Sat, 21 Oct 2023 13:07:26 +0800
Subject: [PATCH 1/2] [SimplifyCFG] Precommit tests for PR65835
---
.../Transforms/SimplifyCFG/switch_mask.ll | 109 ++++++++++++++++++
1 file changed, 109 insertions(+)
create mode 100644 llvm/test/Transforms/SimplifyCFG/switch_mask.ll
diff --git a/llvm/test/Transforms/SimplifyCFG/switch_mask.ll b/llvm/test/Transforms/SimplifyCFG/switch_mask.ll
new file mode 100644
index 000000000000000..8c97a0660d07074
--- /dev/null
+++ b/llvm/test/Transforms/SimplifyCFG/switch_mask.ll
@@ -0,0 +1,109 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=simplifycfg --switch-to-lookup -S < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+; https://alive2.llvm.org/ce/z/tuxLhJ
+define i1 @switch_lookup_with_small_i1(i64 %x) {
+; CHECK-LABEL: @switch_lookup_with_small_i1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[AND:%.*]] = and i64 [[X:%.*]], 15
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i64 [[AND]], 11
+; CHECK-NEXT: [[SWITCH_CAST:%.*]] = trunc i64 [[AND]] to i11
+; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul nuw nsw i11 [[SWITCH_CAST]], 1
+; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i11 -1018, [[SWITCH_SHIFTAMT]]
+; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i11 [[SWITCH_DOWNSHIFT]] to i1
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP0]], i1 [[SWITCH_MASKED]], i1 false
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+entry:
+ %and = and i64 %x, 15
+ switch i64 %and, label %default [
+ i64 10, label %lor.end
+ i64 1, label %lor.end
+ i64 2, label %lor.end
+ ]
+
+default: ; preds = %entry
+ br label %lor.end
+
+lor.end: ; preds = %entry, %entry, %entry, %default
+ %0 = phi i1 [ true, %entry ], [ false, %default ], [ true, %entry ], [ true, %entry ]
+ ret i1 %0
+}
+
+; https://godbolt.org/z/sjbjorKon
+define i8 @switch_lookup_with_small_i8(i64 %x) {
+; CHECK-LABEL: @switch_lookup_with_small_i8(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[REM:%.*]] = urem i64 [[X:%.*]], 5
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i64 [[REM]], 3
+; CHECK-NEXT: [[SWITCH_CAST:%.*]] = trunc i64 [[REM]] to i24
+; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul nuw nsw i24 [[SWITCH_CAST]], 8
+; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i24 460303, [[SWITCH_SHIFTAMT]]
+; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i24 [[SWITCH_DOWNSHIFT]] to i8
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP0]], i8 [[SWITCH_MASKED]], i8 0
+; CHECK-NEXT: ret i8 [[TMP1]]
+;
+entry:
+ %rem = urem i64 %x, 5
+ switch i64 %rem, label %default [
+ i64 0, label %sw.bb0
+ i64 1, label %sw.bb1
+ i64 2, label %sw.bb2
+ ]
+
+sw.bb0: ; preds = %entry
+ br label %lor.end
+
+sw.bb1: ; preds = %entry
+ br label %lor.end
+
+sw.bb2: ; preds = %entry
+ br label %lor.end
+
+default: ; preds = %entry
+ br label %lor.end
+
+lor.end:
+ %0 = phi i8 [ 15, %sw.bb0 ], [ 6, %sw.bb1 ], [ 7, %sw.bb2 ], [ 0, %default ]
+ ret i8 %0
+}
+
+; Negative test: Table size would not fit the register.
+define i8 @switch_lookup_with_small_i8_negative(i64 %x) {
+; CHECK-LABEL: @switch_lookup_with_small_i8_negative(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[REM:%.*]] = urem i64 [[X:%.*]], 9
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i64 [[REM]], 3
+; CHECK-NEXT: [[SWITCH_CAST:%.*]] = trunc i64 [[REM]] to i24
+; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul nuw nsw i24 [[SWITCH_CAST]], 8
+; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i24 460303, [[SWITCH_SHIFTAMT]]
+; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i24 [[SWITCH_DOWNSHIFT]] to i8
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP0]], i8 [[SWITCH_MASKED]], i8 0
+; CHECK-NEXT: ret i8 [[TMP1]]
+;
+entry:
+ %rem = urem i64 %x, 9 ; 9 * 8 = 72 > 64, not fit the register
+ switch i64 %rem, label %default [
+ i64 0, label %sw.bb0
+ i64 1, label %sw.bb1
+ i64 2, label %sw.bb2
+ ]
+
+sw.bb0: ; preds = %entry
+ br label %lor.end
+
+sw.bb1: ; preds = %entry
+ br label %lor.end
+
+sw.bb2: ; preds = %entry
+ br label %lor.end
+
+default: ; preds = %entry
+ br label %lor.end
+
+lor.end:
+ %0 = phi i8 [ 15, %sw.bb0 ], [ 6, %sw.bb1 ], [ 7, %sw.bb2 ], [ 0, %default ]
+ ret i8 %0
+}
>From 451c35c4881dd3892b0cc03785086c1b0736e103 Mon Sep 17 00:00:00 2001
From: zhongyunde 00443407 <zhongyunde at huawei.com>
Date: Fri, 1 Sep 2023 23:05:45 -0400
Subject: [PATCH 2/2] [SimplifyCFG] Delete the unnecessary range check for
small mask operation
When the small mask value little than 64, we can eliminate the checking
for upper limit of the range by enlarge the lookup table size to the maximum
index value. (Then the final table size grows to the next pow2 value)
```
bool f(unsigned x) {
switch (x % 8) {
case 0: return 1;
case 1: return 0;
case 2: return 0;
case 3: return 1;
case 4: return 1;
case 5: return 0;
case 6: return 1;
// This would remove the range check: case 7: return 0;
}
return 0;
}
```
Use WouldFitInRegister instead of fitsInLegalInteger to support
more result type beside bool.
Fixes https://github.com/llvm/llvm-project/issues/65120
---
llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 22 +++++++++++++++--
.../Transforms/SimplifyCFG/switch_mask.ll | 24 ++++++++-----------
2 files changed, 30 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 35fead111aa9666..83f4bdb4cff66c5 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -6598,9 +6598,8 @@ static bool SwitchToLookupTable(SwitchInst *SI, IRBuilder<> &Builder,
// If the default destination is unreachable, or if the lookup table covers
// all values of the conditional variable, branch directly to the lookup table
// BB. Otherwise, check that the condition is within the case range.
- const bool DefaultIsReachable =
+ bool DefaultIsReachable =
!isa<UnreachableInst>(SI->getDefaultDest()->getFirstNonPHIOrDbg());
- const bool GeneratingCoveredLookupTable = (MaxTableSize == TableSize);
// Create the BB that does the lookups.
Module &Mod = *CommonDest->getParent()->getParent();
@@ -6631,6 +6630,25 @@ static bool SwitchToLookupTable(SwitchInst *SI, IRBuilder<> &Builder,
BranchInst *RangeCheckBranch = nullptr;
+ // Grow the table to cover all possible index values to avoid the range check.
+ if (UseSwitchConditionAsTableIndex) {
+ ConstantRange CR = computeConstantRange(TableIndex, /* ForSigned */ false);
+ // Grow the table shouldn't have any size impact by checking
+ // WouldFitInRegister.
+ // TODO: Consider growing the table also when it doesn't fit in a register
+ // if no optsize is specified.
+ if (all_of(ResultTypes, [&](const auto &KV) {
+ return SwitchLookupTable::WouldFitInRegister(
+ DL, CR.getUpper().getLimitedValue(), KV.second /* ResultType */);
+ })) {
+ // The default branch is unreachable when we enlarge the lookup table.
+ // Adjust DefaultIsReachable to reuse code path.
+ TableSize = CR.getUpper().getZExtValue();
+ DefaultIsReachable = false;
+ }
+ }
+
+ const bool GeneratingCoveredLookupTable = (MaxTableSize == TableSize);
if (!DefaultIsReachable || GeneratingCoveredLookupTable) {
Builder.CreateBr(LookupBB);
if (DTU)
diff --git a/llvm/test/Transforms/SimplifyCFG/switch_mask.ll b/llvm/test/Transforms/SimplifyCFG/switch_mask.ll
index 8c97a0660d07074..123519bc6921147 100644
--- a/llvm/test/Transforms/SimplifyCFG/switch_mask.ll
+++ b/llvm/test/Transforms/SimplifyCFG/switch_mask.ll
@@ -8,13 +8,11 @@ define i1 @switch_lookup_with_small_i1(i64 %x) {
; CHECK-LABEL: @switch_lookup_with_small_i1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[AND:%.*]] = and i64 [[X:%.*]], 15
-; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i64 [[AND]], 11
-; CHECK-NEXT: [[SWITCH_CAST:%.*]] = trunc i64 [[AND]] to i11
-; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul nuw nsw i11 [[SWITCH_CAST]], 1
-; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i11 -1018, [[SWITCH_SHIFTAMT]]
-; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i11 [[SWITCH_DOWNSHIFT]] to i1
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP0]], i1 [[SWITCH_MASKED]], i1 false
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[SWITCH_CAST:%.*]] = trunc i64 [[AND]] to i16
+; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul nuw nsw i16 [[SWITCH_CAST]], 1
+; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i16 1030, [[SWITCH_SHIFTAMT]]
+; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i16 [[SWITCH_DOWNSHIFT]] to i1
+; CHECK-NEXT: ret i1 [[SWITCH_MASKED]]
;
entry:
%and = and i64 %x, 15
@@ -37,13 +35,11 @@ define i8 @switch_lookup_with_small_i8(i64 %x) {
; CHECK-LABEL: @switch_lookup_with_small_i8(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[REM:%.*]] = urem i64 [[X:%.*]], 5
-; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i64 [[REM]], 3
-; CHECK-NEXT: [[SWITCH_CAST:%.*]] = trunc i64 [[REM]] to i24
-; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul nuw nsw i24 [[SWITCH_CAST]], 8
-; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i24 460303, [[SWITCH_SHIFTAMT]]
-; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i24 [[SWITCH_DOWNSHIFT]] to i8
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP0]], i8 [[SWITCH_MASKED]], i8 0
-; CHECK-NEXT: ret i8 [[TMP1]]
+; CHECK-NEXT: [[SWITCH_CAST:%.*]] = trunc i64 [[REM]] to i40
+; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul nuw nsw i40 [[SWITCH_CAST]], 8
+; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i40 460303, [[SWITCH_SHIFTAMT]]
+; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i40 [[SWITCH_DOWNSHIFT]] to i8
+; CHECK-NEXT: ret i8 [[SWITCH_MASKED]]
;
entry:
%rem = urem i64 %x, 5
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