[llvm] [AArch64][SVE2] Use rshrnb for masked stores (PR #70026)

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github-actions[bot] wrote:


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git-clang-format --diff febc4ff74a4e0311c3663fa5d690c59f7f692583 5870a4321d4941773b420e55d55efa5ad1c45039 -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 09ab4ddacddf..e09ebe01a336 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -21017,15 +21017,17 @@ static SDValue performMSTORECombine(SDNode *N,
     }
   }
 
-  if (MST->isTruncatingStore()){
-    if (SDValue Rshrnb = trySimplifySrlAddToRshrnb(Value, DAG, Subtarget)){
+  if (MST->isTruncatingStore()) {
+    if (SDValue Rshrnb = trySimplifySrlAddToRshrnb(Value, DAG, Subtarget)) {
       EVT ValueVT = Value->getValueType(0);
       EVT MemVT = MST->getMemoryVT();
       if ((ValueVT == MVT::nxv8i16 && MemVT == MVT::nxv8i8) ||
           (ValueVT == MVT::nxv4i32 && MemVT == MVT::nxv4i16) ||
-          (ValueVT == MVT::nxv2i64 && MemVT == MVT::nxv2i32)){
-        return DAG.getMaskedStore(MST->getChain(), DL, Rshrnb, MST->getBasePtr(), MST->getOffset(), MST->getMask(), 
-                            MST->getMemoryVT(), MST->getMemOperand(), MST->getAddressingMode(), true);
+          (ValueVT == MVT::nxv2i64 && MemVT == MVT::nxv2i32)) {
+        return DAG.getMaskedStore(
+            MST->getChain(), DL, Rshrnb, MST->getBasePtr(), MST->getOffset(),
+            MST->getMask(), MST->getMemoryVT(), MST->getMemOperand(),
+            MST->getAddressingMode(), true);
       }
     }
   }

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https://github.com/llvm/llvm-project/pull/70026