[llvm] [RISCV] Macro-fusion support for veyron-v1 CPU. (PR #70012)

[Wang Pengcheng via llvm-commits]

wangpc-pp wrote:

As far as I know, there may be up to 30+ instruction pairs that can be fused for some macroarchitecture (for example, , [Xiangshan - Decode Unit, Chinese](https://xiangshan-doc.readthedocs.io/zh_CN/latest/frontend/decode/)). If we define subtarget features for all of them, that would be a disaster I think. So, I'm working on a TableGen backend that generates predicators for macro fusion (with some refactor of `ScheduleModel`) and I will raise a RFC and PR later. This is still WIP and  discussions are welcome!

Anyway, this PR looks great to me, and I'm just sharing some information here.

(For current implementation, I don't know if we can refer to PPC's, in which there is a script-generated header.)

https://github.com/llvm/llvm-project/pull/70012