[llvm] [AMDGPU] ISel for @llvm.amdgcn.cs.chain intrinsic (PR #68186)

[via llvm-commits]

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@@ -374,3 +376,425 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24
   call amdgpu_gfx void @use(<24 x i32> %sgprs, <24 x i32> %vgprs)
   ret void
 }
+
+define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %a, <3 x i32> %b) {
+; GISEL-GFX11-LABEL: cs_to_chain:
+; GISEL-GFX11:       ; %bb.0:
+; GISEL-GFX11-NEXT:    v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v10, v2
+; GISEL-GFX11-NEXT:    s_mov_b32 s3, s0
+; GISEL-GFX11-NEXT:    ;;#ASMSTART
+; GISEL-GFX11-NEXT:    s_nop
+; GISEL-GFX11-NEXT:    ;;#ASMEND
+; GISEL-GFX11-NEXT:    s_mov_b32 s0, s3
+; GISEL-GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX11-NEXT:    v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v1
+; GISEL-GFX11-NEXT:    s_mov_b32 exec_lo, -1
+; GISEL-GFX11-NEXT:    s_getpc_b64 s[4:5]
+; GISEL-GFX11-NEXT:    s_add_u32 s4, s4, chain_callee at gotpcrel32@lo+4
+; GISEL-GFX11-NEXT:    s_addc_u32 s5, s5, chain_callee at gotpcrel32@hi+12
+; GISEL-GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x0
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rovka wrote:

Ok, I did that but I think the change for absolute relocations wasn't in yet when I made this PR, so I'd have to either merge or rebase for us to see that. IIUC both have disadvantages in GitHub? I'll upload just the change to the triple for now, since that leads to some other changes too (only in the whole-backend tests, not in the ISel-only tests).

https://github.com/llvm/llvm-project/pull/68186