[llvm] [AMDGPU] - Add s_bitreplicate intrinsic (PR #69209)

[Jessica Del via llvm-commits]

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@@ -6297,6 +6297,14 @@ SIInstrInfo::legalizeOperands(MachineInstr &MI,
     return CreatedBB;
   }
 
+  // Legalize S_BITREPLICATE
+  if (MI.getOpcode() == AMDGPU::S_BITREPLICATE_B64_B32) {
+    MachineOperand &Src = MI.getOperand(1);
+    if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg())))
+      Src.setReg(readlaneVGPRToSGPR(Src.getReg(), MI, MRI));
+    return CreatedBB;
+  }
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OutOfCache wrote:

> Emitting readfirstlane is just wrong, you have to emulate the operation with a VALU expansion if needed

Even with the `convergent` attribute of the intrinsic? I thought we can rule out any divergent inputs with that.

https://github.com/llvm/llvm-project/pull/69209