[llvm] 300190f - [AMDGPU] Regenerate udiv.ll

[via llvm-commits]

Author: pvanhout
Date: 2023-10-24T07:59:41+02:00
New Revision: 300190ffa762d38025344bc001c6b839110497d2

URL: https://github.com/llvm/llvm-project/commit/300190ffa762d38025344bc001c6b839110497d2
DIFF: https://github.com/llvm/llvm-project/commit/300190ffa762d38025344bc001c6b839110497d2.diff

LOG: [AMDGPU] Regenerate udiv.ll

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/udiv.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll
index 0ca8f8aace983c5..10f45b2c8aba01f 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv.ll
@@ -2667,37 +2667,38 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) {
 ; GCN-LABEL: v_test_udiv64_mulhi_fold:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v4, 0xa7c5
-; GCN-NEXT:    v_mul_u32_u24_e32 v3, 0x500, v4
-; GCN-NEXT:    v_mul_hi_u32_u24_e32 v2, 0x500, v4
-; GCN-NEXT:    v_add_u32_e32 v3, vcc, 0x4237, v3
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v2, vcc
-; GCN-NEXT:    v_add_u32_e32 v6, vcc, 0xa9000000, v3
-; GCN-NEXT:    s_mov_b32 s6, 0xfffe7960
-; GCN-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v6, s6, 0
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v5, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, v7, s6
+; GCN-NEXT:    s_mov_b32 s4, 0x346d900
+; GCN-NEXT:    s_add_u32 s4, 0x4237, s4
+; GCN-NEXT:    v_mov_b32_e32 v2, 0xa9000000
+; GCN-NEXT:    v_add_u32_e32 v6, vcc, s4, v2
+; GCN-NEXT:    s_mov_b32 s4, 0xfffe7960
+; GCN-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v6, s4, 0
+; GCN-NEXT:    s_addc_u32 s6, 0, 0
+; GCN-NEXT:    s_cmp_lg_u64 vcc, 0
+; GCN-NEXT:    s_addc_u32 s6, s6, 0xa7c5
+; GCN-NEXT:    s_mul_i32 s4, s6, 0xfffe7960
 ; GCN-NEXT:    v_sub_u32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v8, v6, v2
-; GCN-NEXT:    v_add_u32_e32 v5, vcc, v4, v3
+; GCN-NEXT:    v_add_u32_e32 v5, vcc, s4, v3
 ; GCN-NEXT:    v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 0
-; GCN-NEXT:    v_add_u32_e32 v8, vcc, v8, v3
-; GCN-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v7, v2, 0
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v4, vcc
-; GCN-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v7, v5, 0
-; GCN-NEXT:    v_add_u32_e32 v2, vcc, v8, v2
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v9, v3, vcc
+; GCN-NEXT:    v_mul_hi_u32 v7, v6, v2
+; GCN-NEXT:    v_add_u32_e32 v7, vcc, v7, v3
+; GCN-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], s6, v2, 0
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v4, vcc
+; GCN-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], s6, v5, 0
+; GCN-NEXT:    v_add_u32_e32 v2, vcc, v7, v2
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v8, v3, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_add_u32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT:    v_add_u32_e32 v4, vcc, v6, v2
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v3, vcc
-; GCN-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v0, v5, 0
-; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
+; GCN-NEXT:    v_mov_b32_e32 v4, s6
+; GCN-NEXT:    v_add_u32_e32 v5, vcc, v6, v2
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v3, vcc
+; GCN-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v0, v4, 0
+; GCN-NEXT:    v_mul_hi_u32 v6, v0, v5
 ; GCN-NEXT:    v_add_u32_e32 v6, vcc, v6, v2
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v3, vcc
-; GCN-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v1, v4, 0
-; GCN-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v1, v5, 0
+; GCN-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v1, v5, 0
+; GCN-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v1, v4, 0
 ; GCN-NEXT:    v_add_u32_e32 v2, vcc, v6, v2
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v7, v3, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc