[llvm] 51446d9 - [RISCV] Only check for scalar VT at depth 0 in hasAllNBitUsers.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-10-23T15:05:38-07:00
New Revision: 51446d945adb0ffdbfde4dc85396540c1c650638

URL: https://github.com/llvm/llvm-project/commit/51446d945adb0ffdbfde4dc85396540c1c650638
DIFF: https://github.com/llvm/llvm-project/commit/51446d945adb0ffdbfde4dc85396540c1c650638.diff

LOG: [RISCV] Only check for scalar VT at depth 0 in hasAllNBitUsers.

VTs on already selected instructions can be arbitrary. Reviewing
the isel table I see i32 used for instructions that are part of
multiple instruction output patterns. Looks like tblgen to just
picks the lowest numbered MVT that is legal for the destination
register class of the instruction.

Seems better to just not check types for already selected nodes.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 1b067557b2f9554..81a1304cf1f405e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2880,7 +2880,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
 
   // The PatFrags that call this may run before RISCVGenDAGISel.inc has checked
   // the VT. Ensure the type is scalar to avoid wasting time on vectors.
-  if (!Node->getValueType(0).isScalarInteger())
+  if (Depth == 0 && !Node->getValueType(0).isScalarInteger())
     return false;
 
   for (auto UI = Node->use_begin(), UE = Node->use_end(); UI != UE; ++UI) {