[llvm] [RISCV][GISel] Add ISel support for SHXADD_UW and SLLI.UW (PR #69972)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 23 14:36:45 PDT 2023
================
@@ -150,3 +150,78 @@ body: |
%6:gprb(s64) = G_ADD %5, %1
$x10 = COPY %6(s64)
...
+---
+name: shXadd_uw_complex_shl_and
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: shXadd_uw_complex_shl_and
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 1
+ ; CHECK-NEXT: [[SH2ADD_UW:%[0-9]+]]:gpr = SH2ADD_UW [[SLLI]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[SH2ADD_UW]]
+ %0:gprb(s64) = COPY $x10
+ %1:gprb(s64) = COPY $x11
+
+ %2:gprb(s64) = G_CONSTANT i64 3
+ %3:gprb(s64) = G_SHL %0, %2
+ %4:gprb(s64) = G_CONSTANT i64 17179869183
+ %5:gprb(s64) = G_AND %3, %4
+
+ %6:gprb(s64) = G_ADD %5, %1
+ $x10 = COPY %6(s64)
+...
+---
+name: slli_uw
----------------
topperc wrote:
I think we also need patterns for (shl (i64 (zext (i32 X))), C). SelectionDAG doesn't have that case since i32 isn't a legal type on RV64 there.
https://github.com/llvm/llvm-project/pull/69972
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