[llvm] [llvm][AArch64][Assembly]: Add FP8 instructions assembly and disassembly. (PR #69632)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 23 08:18:31 PDT 2023
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@@ -6056,6 +6056,53 @@ multiclass SIMDThreeSameVectorFML<bit U, bit b13, bits<3> size, string asm,
}
+// FP8 assembly/disassembly classes
+
+//----------------------------------------------------------------------------
+// FP8 Advanced SIMD three-register extension
+//----------------------------------------------------------------------------
+class BaseSIMDThreeVectors<bit Q, bit U, bits<2> size, bits<4> op,
+ RegisterOperand regtype1,
+ RegisterOperand regtype2, string asm,
+ string kind1, string kind2>
+ : I<(outs regtype1:$Rd), (ins regtype2:$Rn, regtype2:$Rm), asm,
+ "\t$Rd" # kind1 # ", $Rn" # kind2 # ", $Rm" # kind2, "", []>, Sched<[]> {
+ bits<5> Rd;
+ bits<5> Rn;
+ bits<5> Rm;
+ let Inst{31} = 0;
+ let Inst{30} = Q;
+ let Inst{29} = U;
+ let Inst{28-24} = 0b01110;
+ let Inst{23-22} = size;
+ let Inst{21} = 0b0;
+ let Inst{20-16} = Rm;
+ let Inst{15} = 0b1;
+ let Inst{14-11} = op;
+ let Inst{10} = 0b1;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Rd;
+}
+
+
+// FCVTN (FP16 to FP8)
+multiclass SIMDThreeSameSizeVectorCvt<string asm> {
+ def v8f8 : BaseSIMDThreeVectors<0b0, 0b0, 0b01, 0b1110, V64, V64, asm, ".8b",".4h">;
+ def v16f8 : BaseSIMDThreeVectors<0b1, 0b0, 0b01, 0b1110, V128, V128, asm, ".16b", ".8h">;
+}
+
+class BaseSIMDThreeSameSizeVectorFP8Tied<bit Q, bits<2> sz, string asm, string kind1,
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CarolineConcatto wrote:
You don't need this class it all can be replaced by :BaseSIMDThreeSameVectorDot
https://github.com/llvm/llvm-project/pull/69632
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