[llvm] [AArch64] Allow SVE code generation for fixed-width vectors (PR #67122)

[David Spickett via llvm-commits]

DavidSpickett wrote:

Did the trick for ARM 32 bit (https://lab.llvm.org/buildbot/#/builders/245/builds/15668), thanks!

https://github.com/llvm/llvm-project/pull/67122