[llvm] [AArch64] Don't generate st2 for 64bit store that can use stp (PR #69901)

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github-actions[bot] wrote:


<!--LLVM CODE FORMAT COMMENT: {clang-format}-->

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git-clang-format --diff ab261eb38a6efaf3f3290400f9f60312aaffff0a d4cbab16748f0b51d739678f22e6b8da63bbf202 -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8cf1f95c8..bff4392b7 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -15355,8 +15355,8 @@ bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI,
   // zip;ldp pair which has higher throughput.
   if (Factor == 2 && SubVecTy->getPrimitiveSizeInBits() == 64 &&
       (Mask[0] != 0 ||
-       hasNearbyPairedStore(SI->getIterator(), SI->getParent()->end(),
-                            BaseAddr, DL) ||
+       hasNearbyPairedStore(SI->getIterator(), SI->getParent()->end(), BaseAddr,
+                            DL) ||
        hasNearbyPairedStore(SI->getReverseIterator(), SI->getParent()->rend(),
                             BaseAddr, DL)))
     return false;

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https://github.com/llvm/llvm-project/pull/69901