[llvm] [AMDGPU][NFCI] Decouple actual register encodings from HWEncoding values. (PR #69452)

[Joe Nash via llvm-commits]

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@@ -1449,27 +1452,23 @@ unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
 }
 
 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
-  using namespace AMDGPU::EncValues;
-
-  unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN;
-  unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX;
+  unsigned TTmpMin = isGFX9Plus() ? 108 : 112;
+  unsigned TTmpMax = isGFX9Plus() ? 123 : 123;
 
   return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
 }
 
 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val,
                                           bool MandatoryLiteral,
                                           unsigned ImmWidth, bool IsFP) const {
-  using namespace AMDGPU::EncValues;
-
   assert(Val < 1024); // enum10
 
   bool IsAGPR = Val & 512;
   Val &= 511;
 
-  if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
-    return createRegOperand(IsAGPR ? getAgprClassId(Width)
-                                   : getVgprClassId(Width), Val - VGPR_MIN);
+  if (Val >= 256) {
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Sisyph wrote:

If VGPR_MIN/ VGPR_MAX is misleading, we should define a new named value or refactor it, not use a raw number. 

https://github.com/llvm/llvm-project/pull/69452