[llvm] [AMDGPU][NFCI] Decouple actual register encodings from HWEncoding values. (PR #69452)

[Joe Nash via llvm-commits]

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@@ -143,11 +149,11 @@ static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr,
 
 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register,
 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC).
-// Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp.
+// Set Imm{8} to 1 (is-VGPR) to decode using 'enum10' from decodeSrcOp.
 // Used by AV_ register classes (AGPR or VGPR only register operands).
 #define DECODE_OPERAND_REG_AV10(RegClass, OpWidth)                             \
-  DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth,                   \
-               Imm | AMDGPU::EncValues::IS_VGPR, false, 0)
+  DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, Imm | 0x100,      \
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Sisyph wrote:

If AMDGPU::EncValues::IS_VGPR is misleading, we should define a new named value, not use a raw number. 

https://github.com/llvm/llvm-project/pull/69452