[llvm] [RISCV] Combine trunc (srl zext (x), zext (y)) to srl (x, umin (y, scalarsizeinbits(y) - 1)) (PR #69092)

[via llvm-commits]

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@@ -14303,6 +14303,27 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
         }
       }
     }
+
+    // Similarly, we can also optimize the zext nodes for the srl here
+    // trunc (srl zext (X), zext (Y)) -> srl (X, umin (Y, scalarsize(Y) - 1))
+    if (Op.getOpcode() == ISD::SRL && Op.hasOneUse()) {
+      SDValue N0 = Op.getOperand(0);
+      SDValue N1 = Op.getOperand(1);
+      if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
+          N1.getOpcode() == ISD::ZERO_EXTEND && N1.hasOneUse()) {
+        SDValue N00 = N0.getOperand(0);
+        SDValue N10 = N1.getOperand(0);
+        if (N00.getValueType().isVector() &&
+            N00.getValueType() == N10.getValueType() &&
+            N->getValueType(0) == N10.getValueType()) {
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LWenH wrote:

Yeach, I think this is still work for for RVV, but it mat be not work for scalar code generation. More precisely, this patch only handle the vector type cases, it only combine the dag nodes for the vector type.  

So, if y > 7, after lowering to RVV instructions, the **vsrl** intruction still only utilize the lg2(sew) bits as the shift amount, which means the maximum shift amount will less than or equal to 7. May be I should change the pull request title to sum up this more precisely, like combine TRUNCATE_VECTOR_VL(srl zext (x), zext (y)) to srl (x, umin (y, scalarsizeinbits(y) - 1)) for **vectory type**.

https://github.com/llvm/llvm-project/pull/69092