[PATCH] D158492: [RISCV] Add CSR RegisterClass and save/restore fcsr in interrupt

[Wang Pengcheng via Phabricator via llvm-commits]

wangpc added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:553
+      SrcReg = RISCV::X5;
+    }
   } else if (RISCV::GPRPF64RegClass.hasSubClassEq(RC)) {
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zixuan-wu wrote:
> Probably it can refer to SPILL_CR like Pseudo in PPC target. Just use Pseudo here and expand later in eliminateFrameIndex where introduce internal virtual GPR, then it would be scavenged later
Thanks, I'll have a try!


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D158492/new/

https://reviews.llvm.org/D158492