[PATCH] D158492: [RISCV] Add CSR RegisterClass and save/restore fcsr in interrupt

[Zixuan Wu via Phabricator via llvm-commits]

zixuan-wu added a comment.

In D158492#4638197 <https://reviews.llvm.org/D158492#4638197>, @asb wrote:

> Left a trivial comment. Not sure on this vs D158396 <https://reviews.llvm.org/D158396> - the logic of the other patch does seem a bit easier to follow as you suggested in your comment there.

I think it's more consistent than D158396 <https://reviews.llvm.org/D158396> if consider CSRs as callee-saved register in one consistent place and infra.



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:553
+      SrcReg = RISCV::X5;
+    }
   } else if (RISCV::GPRPF64RegClass.hasSubClassEq(RC)) {
----------------
Probably it can refer to SPILL_CR like Pseudo in PPC target. Just use Pseudo here and expand later in eliminateFrameIndex where introduce internal virtual GPR, then it would be scavenged later


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https://reviews.llvm.org/D158492