[llvm] [AVR] Support return address intrinsics (PR #67266)

[Emil J via llvm-commits]

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@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=avr | FileCheck %s
+
+declare ptr @llvm.addressofreturnaddress()
+
+define ptr @a() {
+; CHECK-LABEL: a:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r28
+; CHECK-NEXT:    push r29
+; CHECK-NEXT:    in r28, 61
+; CHECK-NEXT:    in r29, 62
+; CHECK-NEXT:    mov r24, r28
+; CHECK-NEXT:    mov r25, r29
+; CHECK-NEXT:    adiw r24, 3
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ekliptik wrote:

The behavior is the same for all `-mcpu` values. There already is `expand<AVR::SPREAD>` which outside of the PR doesn't have a check for some kind of "SP available". This PR does expose it more, so I guess I can include this check. Do I have to check datasheets for each of the supported targets if it has SPH SPL? Or just each AVR family?

https://github.com/llvm/llvm-project/pull/67266