[llvm] [AVR] Support return address intrinsics (PR #67266)

[Ben Shi via llvm-commits]

================
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=avr | FileCheck %s
+
+declare ptr @llvm.addressofreturnaddress()
+
+define ptr @a() {
+; CHECK-LABEL: a:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r28
+; CHECK-NEXT:    push r29
+; CHECK-NEXT:    in r28, 61
+; CHECK-NEXT:    in r29, 62
+; CHECK-NEXT:    mov r24, r28
+; CHECK-NEXT:    mov r25, r29
+; CHECK-NEXT:    adiw r24, 3
----------------
benshi001 wrote:

This is not always true.

1. The PC register has 2-byte length on some earlier AVR devices.
2. The port 61 & 62 are not always available on some earlier AVR devices.

You need to distinguish the result on different devices, such as
```
RUN: llc < %s -mtriple=avr -mcpu=avr2 | FileCheck --check-prefix=AVR2 %s
RUN: llc < %s -mtriple=avr -mcpu=avr6 | FileCheck --check-prefix=AVR6 %s
```

https://github.com/llvm/llvm-project/pull/67266