[llvm] [AMDGPU][GlobalISel] Expand SGPR S1 exts into G_SELECT (PR #68858)

[Jay Foad via llvm-commits]

================
@@ -2556,16 +2556,44 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
   case AMDGPU::G_SEXT:
   case AMDGPU::G_ZEXT:
   case AMDGPU::G_ANYEXT: {
+    Register DstReg = MI.getOperand(0).getReg();
     Register SrcReg = MI.getOperand(1).getReg();
     LLT SrcTy = MRI.getType(SrcReg);
     const bool Signed = Opc == AMDGPU::G_SEXT;
 
+    const LLT S16 = LLT::scalar(16);
+    const LLT S32 = LLT::scalar(32);
+    const LLT S64 = LLT::scalar(64);
+
     assert(OpdMapper.getVRegs(1).empty());
 
     const RegisterBank *SrcBank =
       OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
 
-    Register DstReg = MI.getOperand(0).getReg();
+    LLT SelType = MRI.getType(DstReg);
+
+    // Extending SGPR S1 to S16/32/64.
+    if (SrcBank == &AMDGPU::SGPRRegBank &&
+        MRI.getType(SrcReg) == LLT::scalar(1)) {
+      assert(SelType == S32 || SelType == S16 || SelType == S64);
+      B.setInstrAndDebugLoc(MI);
+
+      Register False = B.buildConstant(SelType, 0).getReg(0);
+      MRI.setRegBank(False, AMDGPU::SGPRRegBank);
+
+      Register True = B.buildConstant(SelType, Signed ? -1 : 1).getReg(0);
+      MRI.setRegBank(True, AMDGPU::SGPRRegBank);
+
+      Register SrcExt = B.buildZExt(SelType, SrcReg).getReg(0);
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jayfoad wrote:

I am confused about whether Src needs to be extended to 32 bits for a scalar G_SELECT - there is a TODO comment about this in `AMDGPURegisterBankInfo::getInstrMapping`. But it surely should not be extended to 64 bits for a 64-bit select?

https://github.com/llvm/llvm-project/pull/68858