[llvm] [AMDGPU][GlobalISel] Expand SGPR S1 exts into G_SELECT (PR #68858)

[Pierre van Houtryve via llvm-commits]

================
@@ -2556,16 +2556,62 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
   case AMDGPU::G_SEXT:
   case AMDGPU::G_ZEXT:
   case AMDGPU::G_ANYEXT: {
+    Register DstReg = MI.getOperand(0).getReg();
     Register SrcReg = MI.getOperand(1).getReg();
     LLT SrcTy = MRI.getType(SrcReg);
     const bool Signed = Opc == AMDGPU::G_SEXT;
 
+    const LLT S16 = LLT::scalar(16);
+    const LLT S32 = LLT::scalar(32);
+    const LLT S64 = LLT::scalar(64);
+
     assert(OpdMapper.getVRegs(1).empty());
 
     const RegisterBank *SrcBank =
       OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
 
-    Register DstReg = MI.getOperand(0).getReg();
+    LLT SelType = MRI.getType(MI.getOperand(0).getReg());
+
+    // Extending SGPR S1 to S16/32/64.
+    if (SrcBank == &AMDGPU::SGPRRegBank &&
+        MRI.getType(SrcReg) == LLT::scalar(1) &&
+        (SelType == S32 || SelType == S16 || SelType == S64)) {
+
+      Register False = B.buildConstant(S32, 0).getReg(0);
+      MRI.setRegBank(False, AMDGPU::SGPRRegBank);
+
+      Register True = Signed ? B.buildConstant(S32, -1).getReg(0)
+                             : B.buildConstant(S32, 1).getReg(0);
+      MRI.setRegBank(True, AMDGPU::SGPRRegBank);
+
+      B.setInstrAndDebugLoc(MI);
+      Register NewReg = MRI.createGenericVirtualRegister(S32);
+      B.buildInstr(AMDGPU::G_ANYEXT, {NewReg}, {MI.getOperand(1).getReg()});
----------------
Pierre-vh wrote:

In theory I think it doesn't matter. The operand isn't really a S32 anyway, it's SCC so only the first bit (which is the bit corresponding to the current wave I believe) matter 

In practice I agree G_ZEXT is better because it's more technically correct, I also see no meaningful code change (other than MIR tests) from using G_ZEXT, so let's go with that.

https://github.com/llvm/llvm-project/pull/68858