[llvm] [Sparc] Replace CMP instructions with InstAlias (NFCI) (PR #66859)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 8 20:23:09 PDT 2023
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/66859
>From 028bd145ae50fd0408e0463f0018af4b90583c18 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Wed, 20 Sep 2023 09:33:43 +0300
Subject: [PATCH 1/2] [Sparc] Replace CMP instructions with InstAlias
According to the manual `cmp` is a synthetic instruction that maps to
`subcc` with %g0 output operand. Make it so.
The change required some changes to instruction selection process. The
reason is that the old CMP did not have an output operand, while setcc
does have one. We want that operand to be %g0. The easiest way to
achieve this seems to be to mark SUBCC with hasPostISelHook and replace
the output operand with %g0 in the corresponding TargetLowering method.
---
llvm/lib/Target/Sparc/SparcISelLowering.cpp | 8 ++++++++
llvm/lib/Target/Sparc/SparcISelLowering.h | 5 ++++-
llvm/lib/Target/Sparc/SparcInstr64Bit.td | 5 +++--
llvm/lib/Target/Sparc/SparcInstrAliases.td | 7 +++++--
llvm/lib/Target/Sparc/SparcInstrInfo.td | 15 +++------------
5 files changed, 23 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 4d1acc9ad1453da..b6afb8d5a6de9f9 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -3642,3 +3642,11 @@ void SparcTargetLowering::insertSSPDeclarations(Module &M) const {
if (!Subtarget->isTargetLinux())
return TargetLowering::insertSSPDeclarations(M);
}
+
+void SparcTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
+ SDNode *Node) const {
+ assert(MI.getOpcode() == SP::SUBCCrr || MI.getOpcode() == SP::SUBCCri);
+ // If the result is dead, replace it with %g0.
+ if (!Node->hasAnyUseOfValue(0))
+ MI.getOperand(0).setReg(SP::G0);
+}
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.h b/llvm/lib/Target/Sparc/SparcISelLowering.h
index b7b48decef3d742..15d09bc9309754b 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.h
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.h
@@ -222,7 +222,10 @@ namespace llvm {
MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
unsigned BROpcode) const;
+
+ void AdjustInstrPostInstrSelection(MachineInstr &MI,
+ SDNode *Node) const override;
};
} // end namespace llvm
-#endif // SPARC_ISELLOWERING_H
+#endif // LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
index 189efc32cb2667c..0823c6cf69e91f0 100644
--- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td
+++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
@@ -65,6 +65,7 @@ def : Pat<(i64 0), (COPY (i64 G0))>,
Requires<[Is64Bit]>;
// The ALU instructions want their simm13 operands as i32 immediates.
+// FIXME: This is no longer true, they are now pointer-sized.
def as_i32imm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
}]>;
@@ -173,8 +174,8 @@ def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd),
(tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;
}
-def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>;
-def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
+def : Pat<(SPcmpicc i64:$lhs, i64:$rhs), (SUBCCrr $lhs, $rhs)>;
+def : Pat<(SPcmpicc i64:$lhs, (i64 simm13:$rhs)), (SUBCCri $lhs, imm:$rhs)>;
def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>;
} // Predicates = [Is64Bit]
diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td b/llvm/lib/Target/Sparc/SparcInstrAliases.td
index 5d247ac641c7332..db4c05cf180622a 100644
--- a/llvm/lib/Target/Sparc/SparcInstrAliases.td
+++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td
@@ -413,10 +413,13 @@ defm : reg_cond_alias<"gez", 0b111>;
// non-alias form, except for the most obvious and clarifying aliases: cmp, jmp,
// call, tst, ret, retl.
-// Note: cmp is handled in SparcInstrInfo.
-// jmp/call/ret/retl have special case handling for output in
+// Note: jmp/call/ret/retl have special case handling for output in
// SparcInstPrinter.cpp
+// cmp rs1, reg_or_imm -> subcc rs1, reg_or_imm, %g0
+def : InstAlias<"cmp $rs1, $rs2", (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2)>;
+def : InstAlias<"cmp $rs1, $imm", (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm)>;
+
// jmp addr -> jmpl addr, %g0
def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>;
def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>;
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 3e814643f39e610..5b1695314e9603e 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -829,23 +829,14 @@ defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;
let Uses = [ICC], Defs = [ICC] in
defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
-let Defs = [ICC] in
+let Defs = [ICC], hasPostISelHook = true in
defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
let Uses = [ICC] in
defm SUBC : F3_12np <"subx", 0b001100>;
-// cmp (from Section A.3) is a specialized alias for subcc
-let Defs = [ICC], rd = 0 in {
- def CMPrr : F3_1<2, 0b010100,
- (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
- "cmp $rs1, $rs2",
- [(SPcmpicc i32:$rs1, i32:$rs2)]>;
- def CMPri : F3_2<2, 0b010100,
- (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
- "cmp $rs1, $simm13",
- [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
-}
+def : Pat<(SPcmpicc i32:$lhs, i32:$rhs), (SUBCCri $lhs, $rhs)>;
+def : Pat<(SPcmpicc i32:$lhs, (i32 simm13:$rhs)), (SUBCCri $lhs, imm:$rhs)>;
// Section B.18 - Multiply Instructions, p. 113
let Defs = [Y] in {
>From d47572d9c6244e785a63c582e4244213c8d17d22 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Mon, 2 Oct 2023 21:45:48 +0300
Subject: [PATCH 2/2] Fix a bug spotted in the review
---
llvm/lib/Target/Sparc/SparcInstrInfo.td | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 5b1695314e9603e..5e792427cca282c 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -222,6 +222,7 @@ def calltarget : Operand<i32> {
}
def simm13Op : Operand<iPTR> {
+ let OperandType = "OPERAND_IMMEDIATE";
let DecoderMethod = "DecodeSIMM13";
let EncoderMethod = "getSImm13OpValue";
}
@@ -835,7 +836,7 @@ let Defs = [ICC], hasPostISelHook = true in
let Uses = [ICC] in
defm SUBC : F3_12np <"subx", 0b001100>;
-def : Pat<(SPcmpicc i32:$lhs, i32:$rhs), (SUBCCri $lhs, $rhs)>;
+def : Pat<(SPcmpicc i32:$lhs, i32:$rhs), (SUBCCrr $lhs, $rhs)>;
def : Pat<(SPcmpicc i32:$lhs, (i32 simm13:$rhs)), (SUBCCri $lhs, imm:$rhs)>;
// Section B.18 - Multiply Instructions, p. 113
More information about the llvm-commits
mailing list