[llvm] [CodeGenPrepare] Transform ldexp into target supported intrinsics (PR #67552)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 7 06:28:23 PDT 2023
https://github.com/huhu233 updated https://github.com/llvm/llvm-project/pull/67552
>From 38c28d09cea3462fe784870f5b82c5c560368e38 Mon Sep 17 00:00:00 2001
From: huhu233 <1293577861 at qq.com>
Date: Sat, 7 Oct 2023 21:18:18 +0800
Subject: [PATCH] [TargetLowering] Lower ldexp into target supported
instructions
There are more efficient implementations for ldexp on different
targets. This patch lowers ldexp into target supported instructions.
---
.../Target/AArch64/AArch64ISelLowering.cpp | 43 ++++
llvm/lib/Target/AArch64/AArch64ISelLowering.h | 1 +
llvm/lib/Target/X86/X86ISelLowering.cpp | 44 ++++
llvm/lib/Target/X86/X86ISelLowering.h | 2 +
llvm/test/CodeGen/AArch64/ldexp.ll | 55 +++++
llvm/test/CodeGen/X86/call-ldexp.ll | 47 ++++
.../X86/fold-int-pow2-with-fmul-or-fdiv.ll | 202 ++++++++----------
7 files changed, 284 insertions(+), 110 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/ldexp.ll
create mode 100644 llvm/test/CodeGen/X86/call-ldexp.ll
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 9cda43e58d27a43..9e8c5da3639b47c 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1642,6 +1642,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
+ if (Subtarget->hasSVE()) {
+ setOperationAction(ISD::FLDEXP, MVT::f64, Custom);
+ setOperationAction(ISD::FLDEXP, MVT::f32, Custom);
+ }
+
PredictableSelectIsExpensive = Subtarget->predictableSelectIsExpensive();
IsStrictFPEnabled = true;
@@ -6217,6 +6222,8 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
case ISD::FSHL:
case ISD::FSHR:
return LowerFunnelShift(Op, DAG);
+ case ISD::FLDEXP:
+ return LowerFLDEXP(Op, DAG);
}
}
@@ -26360,3 +26367,39 @@ bool AArch64TargetLowering::preferScalarizeSplat(SDNode *N) const {
}
return true;
}
+
+SDValue AArch64TargetLowering::LowerFLDEXP(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDValue X = Op.getOperand(0);
+ EVT XScalarTy = X.getValueType();
+ SDValue Exp = Op.getOperand(1);
+
+ SDLoc DL(Op);
+ EVT XVT, ExpVT;
+ switch (Op.getValueSizeInBits()) {
+ default:
+ return SDValue();
+ case 32:
+ XVT = MVT::nxv4f32;
+ ExpVT = MVT::nxv4i32;
+ break;
+ case 64:
+ XVT = MVT::nxv2f64;
+ ExpVT = MVT::nxv2i64;
+ Exp = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Exp);
+ break;
+ }
+
+ SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
+ SDValue VX =
+ DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, XVT, DAG.getUNDEF(XVT), X, Zero);
+ SDValue VExp = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ExpVT,
+ DAG.getUNDEF(ExpVT), Exp, Zero);
+ SDValue VPg = getPTrue(DAG, DL, XVT.changeVectorElementType(MVT::i1),
+ AArch64SVEPredPattern::all);
+ SDValue FScale =
+ DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XVT,
+ DAG.getConstant(Intrinsic::aarch64_sve_fscale, DL, MVT::i64),
+ VPg, VX, VExp);
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, XScalarTy, FScale, Zero);
+}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 9dcfba3a229cccd..c67083a70b0fa02 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1136,6 +1136,7 @@ class AArch64TargetLowering : public TargetLowering {
SDValue LowerFixedLengthFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFixedLengthVECTOR_SHUFFLEToSVE(SDValue Op,
SelectionDAG &DAG) const;
+ SDValue LowerFLDEXP(SDValue Op, SelectionDAG &DAG) const;
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
SmallVectorImpl<SDNode *> &Created) const override;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c4cd2a672fe7b26..64bb3b0881d593d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2395,6 +2395,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i128, Custom);
}
+ if (Subtarget.hasAVX512()) {
+ setOperationAction(ISD::FLDEXP, MVT::f32, Custom);
+ setOperationAction(ISD::FLDEXP, MVT::f64, Custom);
+ }
+
// On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
// is. We should promote the value to 64-bits to solve this.
// This is what the CRT headers do - `fmodf` is an inline header
@@ -31904,6 +31909,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::ADDRSPACECAST: return LowerADDRSPACECAST(Op, DAG);
case X86ISD::CVTPS2PH: return LowerCVTPS2PH(Op, DAG);
case ISD::PREFETCH: return LowerPREFETCH(Op, Subtarget, DAG);
+ case ISD::FLDEXP:
+ return LowerFLDEXP(Op, DAG);
}
}
@@ -57389,3 +57396,40 @@ Align X86TargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
return Align(1ULL << ExperimentalPrefInnermostLoopAlignment);
return TargetLowering::getPrefLoopAlignment();
}
+
+SDValue X86TargetLowering::LowerFLDEXP(SDValue Op, SelectionDAG &DAG) const {
+ SDValue X = Op.getOperand(0);
+ EVT XScalarTy = X.getValueType();
+ SDValue Exp = Op.getOperand(1);
+
+ SDLoc DL(Op);
+ EVT XVT, ExpVT;
+ SDValue IID;
+ switch (Op.getValueSizeInBits()) {
+ default:
+ return SDValue();
+ case 32:
+ XVT = MVT::v4f32;
+ ExpVT = MVT::v4f32;
+ IID = DAG.getConstant(Intrinsic::x86_avx512_mask_scalef_ss, DL, MVT::i64);
+ break;
+ case 64:
+ XVT = MVT::v2f64;
+ ExpVT = MVT::v2f64;
+ IID = DAG.getConstant(Intrinsic::x86_avx512_mask_scalef_sd, DL, MVT::i64);
+ break;
+ }
+
+ SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
+ Exp = DAG.getNode(ISD::SINT_TO_FP, DL, XScalarTy, Exp);
+ SDValue VX =
+ DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, XVT, DAG.getUNDEF(XVT), X, Zero);
+ SDValue VExp = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ExpVT,
+ DAG.getUNDEF(ExpVT), Exp, Zero);
+ SDValue Pg = DAG.getConstant(-1, DL, MVT::i8);
+ // _MM_FROUND_CUR_DIRECTION (4, no rounding).
+ SDValue Round = DAG.getConstant(4, DL, MVT::i32);
+ SDValue Scalef = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XVT,
+ {IID, VX, VExp, VX, Pg, Round});
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, XScalarTy, Scalef, Zero);
+}
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 8046f42736951cd..26a9d0e10d4578f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -1700,6 +1700,8 @@ namespace llvm {
const SmallVectorImpl<SDValue> &OutVals,
const SDLoc &dl, SelectionDAG &DAG) const override;
+ SDValue LowerFLDEXP(SDValue Op, SelectionDAG &DAG) const;
+
bool supportSplitCSR(MachineFunction *MF) const override {
return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
diff --git a/llvm/test/CodeGen/AArch64/ldexp.ll b/llvm/test/CodeGen/AArch64/ldexp.ll
new file mode 100644
index 000000000000000..5aeef30bc3d53e4
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/ldexp.ll
@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -O3 -mtriple=aarch64 -mattr=+sve < %s -o - | FileCheck %s
+
+define dso_local nofpclass(nan inf) double @testExp(double noundef nofpclass(nan inf) %val, i32 noundef %a) {
+; CHECK-LABEL: testExp:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sxtw x8, w0
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: fscale z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT: ret
+entry:
+ %call = tail call fast nofpclass(nan inf) double @ldexp(double noundef nofpclass(nan inf) %val, i32 noundef %a)
+ ret double %call
+}
+
+declare nofpclass(nan inf) double @ldexp(double noundef nofpclass(nan inf), i32 noundef) #1
+
+define dso_local nofpclass(nan inf) float @testExpf(float noundef nofpclass(nan inf) %val, i32 noundef %a) {
+; CHECK-LABEL: testExpf:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fmov s1, w0
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0
+; CHECK-NEXT: fscale z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-NEXT: ret
+entry:
+ %call = tail call fast nofpclass(nan inf) float @ldexpf(float noundef nofpclass(nan inf) %val, i32 noundef %a)
+ ret float %call
+}
+
+declare nofpclass(nan inf) float @ldexpf(float noundef nofpclass(nan inf), i32 noundef) #1
+
+define dso_local nofpclass(nan inf) fp128 @testExpl(fp128 noundef nofpclass(nan inf) %val, i32 noundef %a) {
+; CHECK-LABEL: testExpl:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl ldexpl
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
+entry:
+ %call = tail call fast nofpclass(nan inf) fp128 @ldexpl(fp128 noundef nofpclass(nan inf) %val, i32 noundef %a)
+ ret fp128 %call
+}
+
+declare nofpclass(nan inf) fp128 @ldexpl(fp128 noundef nofpclass(nan inf), i32 noundef) #1
+
+attributes #1 = { mustprogress nofree nosync nounwind willreturn memory(none) }
+
diff --git a/llvm/test/CodeGen/X86/call-ldexp.ll b/llvm/test/CodeGen/X86/call-ldexp.ll
new file mode 100644
index 000000000000000..18fd55b5635b64c
--- /dev/null
+++ b/llvm/test/CodeGen/X86/call-ldexp.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -O3 -mtriple=x86_64 -mattr=+avx512f < %s -o - | FileCheck %s
+
+define dso_local nofpclass(nan inf) double @testExp(double noundef nofpclass(nan inf) %val, i32 noundef %a) {
+; CHECK-LABEL: testExp:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vcvtsi2sd %edi, %xmm1, %xmm1
+; CHECK-NEXT: vscalefsd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: retq
+entry:
+ %call = tail call fast nofpclass(nan inf) double @ldexp(double noundef nofpclass(nan inf) %val, i32 noundef %a)
+ ret double %call
+}
+
+declare nofpclass(nan inf) double @ldexp(double noundef nofpclass(nan inf), i32 noundef) #1
+
+define dso_local nofpclass(nan inf) float @testExpf(float noundef nofpclass(nan inf) %val, i32 noundef %a) {
+; CHECK-LABEL: testExpf:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vcvtsi2ss %edi, %xmm1, %xmm1
+; CHECK-NEXT: vscalefss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: retq
+entry:
+ %call = tail call fast nofpclass(nan inf) float @ldexpf(float noundef nofpclass(nan inf) %val, i32 noundef %a)
+ ret float %call
+}
+
+declare nofpclass(nan inf) float @ldexpf(float noundef nofpclass(nan inf), i32 noundef) #1
+
+define dso_local nofpclass(nan inf) fp128 @testExpl(fp128 noundef nofpclass(nan inf) %val, i32 noundef %a) {
+; CHECK-LABEL: testExpl:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: callq ldexpl at PLT
+; CHECK-NEXT: popq %rax
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
+entry:
+ %call = tail call fast nofpclass(nan inf) fp128 @ldexpl(fp128 noundef nofpclass(nan inf) %val, i32 noundef %a)
+ ret fp128 %call
+}
+
+declare nofpclass(nan inf) fp128 @ldexpl(fp128 noundef nofpclass(nan inf), i32 noundef) #1
+
+attributes #1 = { mustprogress nofree nosync nounwind willreturn memory(none) }
+
diff --git a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
index 8d98ec7eaac2a4c..7c0b7e2aa8d2609 100644
--- a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
+++ b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
@@ -79,38 +79,38 @@ define <4 x float> @fmul_pow2_ldexp_4xfloat(<4 x i32> %i) {
; CHECK-SSE-NEXT: .cfi_def_cfa_offset 8
; CHECK-SSE-NEXT: retq
;
-; CHECK-AVX-LABEL: fmul_pow2_ldexp_4xfloat:
-; CHECK-AVX: # %bb.0:
-; CHECK-AVX-NEXT: subq $40, %rsp
-; CHECK-AVX-NEXT: .cfi_def_cfa_offset 48
-; CHECK-AVX-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-AVX-NEXT: vextractps $1, %xmm0, %edi
-; CHECK-AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-AVX-NEXT: callq ldexpf at PLT
-; CHECK-AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-AVX-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; CHECK-AVX-NEXT: vmovd %xmm0, %edi
-; CHECK-AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-AVX-NEXT: callq ldexpf at PLT
-; CHECK-AVX-NEXT: vinsertps $16, (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
-; CHECK-AVX-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[2,3]
-; CHECK-AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; CHECK-AVX-NEXT: vextractps $2, %xmm0, %edi
-; CHECK-AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-AVX-NEXT: callq ldexpf at PLT
-; CHECK-AVX-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
-; CHECK-AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0],xmm1[3]
-; CHECK-AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; CHECK-AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; CHECK-AVX-NEXT: vextractps $3, %xmm0, %edi
-; CHECK-AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-AVX-NEXT: callq ldexpf at PLT
-; CHECK-AVX-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
-; CHECK-AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
-; CHECK-AVX-NEXT: addq $40, %rsp
-; CHECK-AVX-NEXT: .cfi_def_cfa_offset 8
-; CHECK-AVX-NEXT: retq
+; CHECK-AVX2-LABEL: fmul_pow2_ldexp_4xfloat:
+; CHECK-AVX2: # %bb.0:
+; CHECK-AVX2-NEXT: subq $40, %rsp
+; CHECK-AVX2-NEXT: .cfi_def_cfa_offset 48
+; CHECK-AVX2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-AVX2-NEXT: vextractps $1, %xmm0, %edi
+; CHECK-AVX2-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-AVX2-NEXT: callq ldexpf at PLT
+; CHECK-AVX2-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-AVX2-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-AVX2-NEXT: vmovd %xmm0, %edi
+; CHECK-AVX2-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-AVX2-NEXT: callq ldexpf at PLT
+; CHECK-AVX2-NEXT: vinsertps $16, (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
+; CHECK-AVX2-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[2,3]
+; CHECK-AVX2-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-AVX2-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-AVX2-NEXT: vextractps $2, %xmm0, %edi
+; CHECK-AVX2-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-AVX2-NEXT: callq ldexpf at PLT
+; CHECK-AVX2-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0],xmm1[3]
+; CHECK-AVX2-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-AVX2-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-AVX2-NEXT: vextractps $3, %xmm0, %edi
+; CHECK-AVX2-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-AVX2-NEXT: callq ldexpf at PLT
+; CHECK-AVX2-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
+; CHECK-AVX2-NEXT: addq $40, %rsp
+; CHECK-AVX2-NEXT: .cfi_def_cfa_offset 8
+; CHECK-AVX2-NEXT: retq
%r = call <4 x float> @llvm.ldexp.v4f32.v4i32(<4 x float> <float 9.000000e+00, float 9.000000e+00, float 9.000000e+00, float 9.000000e+00>, <4 x i32> %i)
ret <4 x float> %r
}
@@ -648,88 +648,70 @@ define <8 x half> @fmul_pow2_ldexp_8xhalf(<8 x i16> %i) {
;
; CHECK-AVX512F-LABEL: fmul_pow2_ldexp_8xhalf:
; CHECK-AVX512F: # %bb.0:
-; CHECK-AVX512F-NEXT: subq $72, %rsp
-; CHECK-AVX512F-NEXT: .cfi_def_cfa_offset 80
-; CHECK-AVX512F-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
-; CHECK-AVX512F-NEXT: vpextrw $7, %xmm0, %edi
-; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-AVX512F-NEXT: callq ldexpf at PLT
-; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vmovd %xmm0, %eax
-; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-AVX512F-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX512F-NEXT: vpextrw $6, %xmm0, %edi
-; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-AVX512F-NEXT: callq ldexpf at PLT
-; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vmovd %xmm0, %eax
-; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
-; CHECK-AVX512F-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
-; CHECK-AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-AVX512F-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX512F-NEXT: vpextrw $5, %xmm0, %edi
-; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-AVX512F-NEXT: callq ldexpf at PLT
-; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vmovd %xmm0, %eax
-; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-AVX512F-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX512F-NEXT: vpextrw $4, %xmm0, %edi
-; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-AVX512F-NEXT: callq ldexpf at PLT
-; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vmovd %xmm0, %eax
-; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
-; CHECK-AVX512F-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
-; CHECK-AVX512F-NEXT: vpunpckldq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
-; CHECK-AVX512F-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
-; CHECK-AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-AVX512F-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX512F-NEXT: vpextrw $3, %xmm0, %edi
-; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-AVX512F-NEXT: callq ldexpf at PLT
-; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vmovd %xmm0, %eax
-; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-AVX512F-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX512F-NEXT: vpextrw $2, %xmm0, %edi
-; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-AVX512F-NEXT: callq ldexpf at PLT
-; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vmovd %xmm0, %eax
-; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
-; CHECK-AVX512F-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
-; CHECK-AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-AVX512F-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX512F-NEXT: vpextrw $1, %xmm0, %edi
-; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-AVX512F-NEXT: callq ldexpf at PLT
-; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vmovd %xmm0, %eax
-; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-AVX512F-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-AVX512F-NEXT: vpextrw $7, %xmm0, %eax
+; CHECK-AVX512F-NEXT: cwtl
+; CHECK-AVX512F-NEXT: vcvtsi2ss %eax, %xmm1, %xmm2
+; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; CHECK-AVX512F-NEXT: vscalefss %xmm2, %xmm1, %xmm2
+; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm2, %xmm2
+; CHECK-AVX512F-NEXT: vmovd %xmm2, %eax
+; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm2
+; CHECK-AVX512F-NEXT: vpextrw $6, %xmm0, %eax
+; CHECK-AVX512F-NEXT: cwtl
+; CHECK-AVX512F-NEXT: vcvtsi2ss %eax, %xmm3, %xmm3
+; CHECK-AVX512F-NEXT: vscalefss %xmm3, %xmm1, %xmm3
+; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm3, %xmm3
+; CHECK-AVX512F-NEXT: vmovd %xmm3, %eax
+; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm3
+; CHECK-AVX512F-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]
+; CHECK-AVX512F-NEXT: vpextrw $5, %xmm0, %eax
+; CHECK-AVX512F-NEXT: cwtl
+; CHECK-AVX512F-NEXT: vcvtsi2ss %eax, %xmm4, %xmm3
+; CHECK-AVX512F-NEXT: vscalefss %xmm3, %xmm1, %xmm3
+; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm3, %xmm3
+; CHECK-AVX512F-NEXT: vmovd %xmm3, %eax
+; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm3
+; CHECK-AVX512F-NEXT: vpextrw $4, %xmm0, %eax
+; CHECK-AVX512F-NEXT: cwtl
+; CHECK-AVX512F-NEXT: vcvtsi2ss %eax, %xmm4, %xmm4
+; CHECK-AVX512F-NEXT: vscalefss %xmm4, %xmm1, %xmm4
+; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm4, %xmm4
+; CHECK-AVX512F-NEXT: vmovd %xmm4, %eax
+; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm4
+; CHECK-AVX512F-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; CHECK-AVX512F-NEXT: vpunpckldq {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; CHECK-AVX512F-NEXT: vpextrw $3, %xmm0, %eax
+; CHECK-AVX512F-NEXT: cwtl
+; CHECK-AVX512F-NEXT: vcvtsi2ss %eax, %xmm5, %xmm3
+; CHECK-AVX512F-NEXT: vscalefss %xmm3, %xmm1, %xmm3
+; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm3, %xmm3
+; CHECK-AVX512F-NEXT: vmovd %xmm3, %eax
+; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm3
+; CHECK-AVX512F-NEXT: vpextrw $2, %xmm0, %eax
+; CHECK-AVX512F-NEXT: cwtl
+; CHECK-AVX512F-NEXT: vcvtsi2ss %eax, %xmm5, %xmm4
+; CHECK-AVX512F-NEXT: vscalefss %xmm4, %xmm1, %xmm4
+; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm4, %xmm4
+; CHECK-AVX512F-NEXT: vmovd %xmm4, %eax
+; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm4
+; CHECK-AVX512F-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; CHECK-AVX512F-NEXT: vpextrw $1, %xmm0, %eax
+; CHECK-AVX512F-NEXT: cwtl
+; CHECK-AVX512F-NEXT: vcvtsi2ss %eax, %xmm5, %xmm4
+; CHECK-AVX512F-NEXT: vscalefss %xmm4, %xmm1, %xmm4
+; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm4, %xmm4
+; CHECK-AVX512F-NEXT: vmovd %xmm4, %eax
+; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm4
; CHECK-AVX512F-NEXT: vmovd %xmm0, %eax
-; CHECK-AVX512F-NEXT: movzwl %ax, %edi
-; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-AVX512F-NEXT: callq ldexpf at PLT
+; CHECK-AVX512F-NEXT: cwtl
+; CHECK-AVX512F-NEXT: vcvtsi2ss %eax, %xmm5, %xmm0
+; CHECK-AVX512F-NEXT: vscalefss %xmm0, %xmm1, %xmm0
; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; CHECK-AVX512F-NEXT: vmovd %xmm0, %eax
; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0
-; CHECK-AVX512F-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
-; CHECK-AVX512F-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
-; CHECK-AVX512F-NEXT: vpunpckldq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
-; CHECK-AVX512F-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
-; CHECK-AVX512F-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
-; CHECK-AVX512F-NEXT: # xmm0 = xmm0[0],mem[0]
-; CHECK-AVX512F-NEXT: addq $72, %rsp
-; CHECK-AVX512F-NEXT: .cfi_def_cfa_offset 8
+; CHECK-AVX512F-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]
+; CHECK-AVX512F-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
+; CHECK-AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; CHECK-AVX512F-NEXT: retq
%r = call <8 x half> @llvm.ldexp.v8f16.v8i16(<8 x half> <half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000>, <8 x i16> %i)
ret <8 x half> %r
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