[llvm] [X86] Enable bfloat type support in inline assembly constraints (PR #68469)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-x86

<details>
<summary>Changes</summary>

Similar to FP16 but we don't have native scalar instruction support, so limit it to vector types only.

Fixes #<!-- -->68149

---
Full diff: https://github.com/llvm/llvm-project/pull/68469.diff


2 Files Affected:

- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+24) 
- (modified) llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll (+12-1) 


``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c4cd2a672fe7b26..c0e93da877a8a10 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -56904,6 +56904,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         if (!Subtarget.hasFP16())
           break;
         [[fallthrough]];
+      case MVT::v8bf16:
+        if (!Subtarget.hasBF16())
+          break;
+        [[fallthrough]];
       case MVT::f128:
       case MVT::v16i8:
       case MVT::v8i16:
@@ -56919,6 +56923,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         if (!Subtarget.hasFP16())
           break;
         [[fallthrough]];
+      case MVT::v16bf16:
+        if (!Subtarget.hasBF16())
+          break;
+        [[fallthrough]];
       case MVT::v32i8:
       case MVT::v16i16:
       case MVT::v8i32:
@@ -56934,6 +56942,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         if (!Subtarget.hasFP16())
           break;
         [[fallthrough]];
+      case MVT::v32bf16:
+        if (!Subtarget.hasBF16())
+          break;
+        [[fallthrough]];
       case MVT::v64i8:
       case MVT::v32i16:
       case MVT::v8f64:
@@ -56977,6 +56989,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         if (!Subtarget.hasFP16())
           break;
         [[fallthrough]];
+      case MVT::v8bf16:
+        if (!Subtarget.hasBF16())
+          break;
+        [[fallthrough]];
       case MVT::f128:
       case MVT::v16i8:
       case MVT::v8i16:
@@ -56990,6 +57006,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         if (!Subtarget.hasFP16())
           break;
         [[fallthrough]];
+      case MVT::v16bf16:
+        if (!Subtarget.hasBF16())
+          break;
+        [[fallthrough]];
       case MVT::v32i8:
       case MVT::v16i16:
       case MVT::v8i32:
@@ -57003,6 +57023,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         if (!Subtarget.hasFP16())
           break;
         [[fallthrough]];
+      case MVT::v32bf16:
+        if (!Subtarget.hasBF16())
+          break;
+        [[fallthrough]];
       case MVT::v64i8:
       case MVT::v32i16:
       case MVT::v8f64:
diff --git a/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll b/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
index fcea55c47cd3ec4..e153387d16e72b1 100644
--- a/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
+++ b/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
@@ -1,7 +1,7 @@
 ; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f -stop-after=finalize-isel > %t 2> %t.err
 ; RUN: FileCheck < %t %s
 ; RUN: FileCheck --check-prefix=CHECK-STDERR < %t.err %s
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16 -stop-after=finalize-isel | FileCheck --check-prefixes=CHECK,FP16 %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512bf16,avx512fp16 -stop-after=finalize-isel | FileCheck --check-prefixes=CHECK,FP16 %s
 
 ; CHECK-LABEL: name: mask_Yk_i8
 ; CHECK: %[[REG1:.*]]:vr512_0_15 = COPY %1
@@ -24,3 +24,14 @@ entry:
   %0 = tail call <32 x half> asm "vaddph\09$3, $2, $0 {$1}", "=x,^Yk,x,x,~{dirflag},~{fpsr},~{flags}"(i8 %msk, <32 x half> %x, <32 x half> %y)
   ret <32 x half> %0
 }
+
+; FP16-LABEL: name: mask_Yk_bf16
+; FP16: %[[REG1:.*]]:vr512_0_15 = COPY %1
+; FP16: %[[REG2:.*]]:vr512_0_15 = COPY %2
+; FP16: INLINEASM &"vaddph\09$3, $2, $0 {$1}", 0 /* attdialect */, {{.*}}, def %{{.*}}, {{.*}}, %{{.*}}, {{.*}}, %[[REG1]], {{.*}}, %[[REG2]], 12 /* clobber */, implicit-def early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def early-clobber $eflags
+; CHECK-STDERR: couldn't allocate output register for constraint 'x'
+define <32 x bfloat> @mask_Yk_bf16(i8 signext %msk, <32 x bfloat> %x, <32 x bfloat> %y) {
+entry:
+  %0 = tail call <32 x bfloat> asm "vaddph\09$3, $2, $0 {$1}", "=x,^Yk,x,x,~{dirflag},~{fpsr},~{flags}"(i8 %msk, <32 x bfloat> %x, <32 x bfloat> %y)
+  ret <32 x bfloat> %0
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/68469