[llvm] ee9f96b - [RISCV][GISel] Add FPR register bank.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-10-06T22:16:36-07:00
New Revision: ee9f96bdd115e1e726e2708d791530c4d686dad2

URL: https://github.com/llvm/llvm-project/commit/ee9f96bdd115e1e726e2708d791530c4d686dad2
DIFF: https://github.com/llvm/llvm-project/commit/ee9f96bdd115e1e726e2708d791530c4d686dad2.diff

LOG: [RISCV][GISel] Add FPR register bank.

We need this so isel can use getRegBankFromRegClass to disambiguate
FSW and SW patterns without depending on pattern order in the tablegen
source files.

While there, add a few missing GPR register classes and sort them
in the order they appear in the tblgen output file.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 63686bd4bdbc3ae..e2cf461a1eb8e22 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -67,17 +67,25 @@ RISCVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
   default:
     llvm_unreachable("Register class not supported");
   case RISCV::GPRRegClassID:
+  case RISCV::GPRF16RegClassID:
+  case RISCV::GPRF32RegClassID:
   case RISCV::GPRNoX0RegClassID:
   case RISCV::GPRNoX0X2RegClassID:
+  case RISCV::GPRJALRRegClassID:
   case RISCV::GPRTCRegClassID:
-  case RISCV::GPRCRegClassID:
   case RISCV::GPRC_and_GPRTCRegClassID:
+  case RISCV::GPRCRegClassID:
   case RISCV::GPRC_and_SR07RegClassID:
-  case RISCV::GPRX0RegClassID:
-  case RISCV::GPRJALRRegClassID:
-  case RISCV::SPRegClassID:
   case RISCV::SR07RegClassID:
+  case RISCV::SPRegClassID:
+  case RISCV::GPRX0RegClassID:
     return getRegBank(RISCV::GPRRegBankID);
+  case RISCV::FPR64RegClassID:
+  case RISCV::FPR16RegClassID:
+  case RISCV::FPR32RegClassID:
+  case RISCV::FPR64CRegClassID:
+  case RISCV::FPR32CRegClassID:
+    return getRegBank(RISCV::FPRRegBankID);
   }
 }
 

diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td
index b49f8259e382beb..49f18e19c2269fd 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td
@@ -11,3 +11,6 @@
 
 /// General Purpose Registers: X.
 def GPRRegBank : RegisterBank<"GPRB", [GPR]>;
+
+/// Floating Point Registers: F.
+def FPRRegBank : RegisterBank<"FPRB", [FPR64]>;