[llvm] [RISCV][GlobalISel] Select G_GLOBAL_VALUE for medlow code model (PR #68380)
Nitin John Raj via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 6 13:54:02 PDT 2023
https://github.com/nitinjohnraj updated https://github.com/llvm/llvm-project/pull/68380
>From f0a3b4f84ca0eed0365ad4d46589def8f0a49e91 Mon Sep 17 00:00:00 2001
From: Nitin John Raj <nitin.raj at sifive.com>
Date: Thu, 5 Oct 2023 21:18:16 -0700
Subject: [PATCH 1/4] [RISCV][GlobalISel] Select G_GLOBAL_VALUE
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 3 ++-
llvm/lib/Target/RISCV/RISCVGISel.td | 20 +++++++++++++++++++
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4f97a0d84f686f9..580c9100e95c29b 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -63,6 +63,7 @@ class RISCVInstructionSelector : public InstructionSelector {
const RISCVInstrInfo &TII;
const RISCVRegisterInfo &TRI;
const RISCVRegisterBankInfo &RBI;
+ const RISCVTargetMachine &TM;
// FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel
// uses "STI." in the code generated by TableGen. We need to unify the name of
@@ -87,7 +88,7 @@ class RISCVInstructionSelector : public InstructionSelector {
RISCVInstructionSelector::RISCVInstructionSelector(
const RISCVTargetMachine &TM, const RISCVSubtarget &STI,
const RISCVRegisterBankInfo &RBI)
- : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI),
+ : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM),
#define GET_GLOBALISEL_PREDICATES_INIT
#include "RISCVGenGlobalISel.inc"
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 8059b517f26ba3c..490f799b82a5e4f 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -16,6 +16,26 @@
include "RISCV.td"
include "RISCVCombine.td"
+class RISCVGenericInstruction : GenericInstruction {
+ let Namespace = "RISCV";
+}
+
+// A pseudo to represent a relocatable add instruction as part of address
+// computation.
+def G_ADD_LO : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type1:$src, type2:$imm);
+ let hasSideEffects = 0;
+}
+def : GINodeEquiv<G_ADD_LO, riscv_add_lo>;
+
+def G_HI : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type1:$imm);
+ let hasSideEffects = 0;
+}
+def : GINodeEquiv<G_HI, riscv_hi>;
+
def simm12Plus1 : ImmLeaf<XLenVT, [{
return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
>From 78bf6ddd812de4da8bcf45218299974f48dc02fd Mon Sep 17 00:00:00 2001
From: Nitin John Raj <nitin.raj at sifive.com>
Date: Fri, 6 Oct 2023 13:04:41 -0700
Subject: [PATCH 2/4] Move functionality from ISelLowering to select + Delete
new generic instructions
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 39 ++++++++++++++++++-
llvm/lib/Target/RISCV/RISCVGISel.td | 20 ----------
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 22 +++++++++++
3 files changed, 60 insertions(+), 21 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 580c9100e95c29b..a63e9d111d9d17d 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -48,6 +48,8 @@ class RISCVInstructionSelector : public InstructionSelector {
bool selectCopy(MachineInstr &MI, MachineRegisterInfo &MRI) const;
bool selectConstant(MachineInstr &MI, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) const;
+ bool selectGlobalValue(MachineInstr &MI, MachineIRBuilder &MIB,
+ MachineRegisterInfo &MRI) const;
bool selectSExtInreg(MachineInstr &MI, MachineIRBuilder &MIB) const;
bool earlySelectShift(unsigned Opc, MachineInstr &I, MachineIRBuilder &MIB,
@@ -88,7 +90,8 @@ class RISCVInstructionSelector : public InstructionSelector {
RISCVInstructionSelector::RISCVInstructionSelector(
const RISCVTargetMachine &TM, const RISCVSubtarget &STI,
const RISCVRegisterBankInfo &RBI)
- : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM),
+ : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI),
+ TM(TM),
#define GET_GLOBALISEL_PREDICATES_INIT
#include "RISCVGenGlobalISel.inc"
@@ -230,6 +233,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
return selectCopy(MI, MRI);
case TargetOpcode::G_CONSTANT:
return selectConstant(MI, MIB, MRI);
+ case TargetOpcode::G_GLOBAL_VALUE:
+ return selectGlobalValue(MI, MIB, MRI);
case TargetOpcode::G_BRCOND: {
// TODO: Fold with G_ICMP.
auto Bcc =
@@ -354,6 +359,38 @@ bool RISCVInstructionSelector::selectConstant(MachineInstr &MI,
return true;
}
+bool RISCVInstructionSelector::selectGlobalValue(MachineInstr &MI, MachineIRBuilder &MIB,
+ MachineRegisterInfo &MRI) const {
+ assert(MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE &&
+ "Wrong selector used!");
+
+ switch (TM.getCodeModel()) {
+ case CodeModel::Small: {
+ Register DstReg = MI.getOperand(0).getReg();
+ const GlobalValue *GV = MI.getOperand(1).getGlobal();
+ Register TmpReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+ MachineInstr *Result =
+ MIB.buildInstr(RISCV::LUI).addDef(TmpReg).addGlobalAddress(GV, 0, RISCVII::MO_HI);
+
+ if (!constrainSelectedInstRegOperands(*Result, TII, TRI, RBI))
+ return false;
+
+ Result = MIB.buildInstr(RISCV::ADDI)
+ .addDef(DstReg)
+ .addReg(TmpReg)
+ .addGlobalAddress(GV, 0, RISCVII::MO_LO);
+
+ if (!constrainSelectedInstRegOperands(*Result, TII, TRI, RBI))
+ return false;
+
+ MI.eraseFromParent();
+ return true;
+ }
+ default:
+ return false;
+ }
+}
+
bool RISCVInstructionSelector::selectSExtInreg(MachineInstr &MI,
MachineIRBuilder &MIB) const {
if (!STI.isRV64())
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 490f799b82a5e4f..8059b517f26ba3c 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -16,26 +16,6 @@
include "RISCV.td"
include "RISCVCombine.td"
-class RISCVGenericInstruction : GenericInstruction {
- let Namespace = "RISCV";
-}
-
-// A pseudo to represent a relocatable add instruction as part of address
-// computation.
-def G_ADD_LO : RISCVGenericInstruction {
- let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type1:$src, type2:$imm);
- let hasSideEffects = 0;
-}
-def : GINodeEquiv<G_ADD_LO, riscv_add_lo>;
-
-def G_HI : RISCVGenericInstruction {
- let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type1:$imm);
- let hasSideEffects = 0;
-}
-def : GINodeEquiv<G_HI, riscv_hi>;
-
def simm12Plus1 : ImmLeaf<XLenVT, [{
return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index abbeff78b6e2864..3e1a3ec108b679d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2032,6 +2032,28 @@ def : Pat<(binop_allwusers<add> GPR:$rs1, (AddiPair:$rs2)),
(AddiPairImmSmall AddiPair:$rs2))>;
}
+//===----------------------------------------------------------------------===//
+// GlobalISel generic instruction definitions
+/* /===----------------------------------------------------------------------===//
+
+class RISCVGenericInstruction : GenericInstruction {
+ let Namespace = "RISCV";
+}
+
+def G_ADD_LO : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type1:$src, type2:$imm);
+ let hasSideEffects = 0;
+}
+def : GINodeEquiv<G_ADD_LO, riscv_add_lo>;
+
+def G_HI : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type1:$imm);
+ let hasSideEffects = 0;
+}
+def : GINodeEquiv<G_HI, riscv_hi>;
+*/
//===----------------------------------------------------------------------===//
// Standard extensions
//===----------------------------------------------------------------------===//
>From 26807f01af7f8559dd5e796db551e4eef4afd913 Mon Sep 17 00:00:00 2001
From: Nitin John Raj <nitin.raj at sifive.com>
Date: Fri, 6 Oct 2023 13:05:21 -0700
Subject: [PATCH 3/4] Add Test
---
.../instruction-select/global-value-rv32.mir | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/global-value-rv32.mir
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/global-value-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/global-value-rv32.mir
new file mode 100644
index 000000000000000..22d339b8a9a0858
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/global-value-rv32.mir
@@ -0,0 +1,40 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck --check-prefix=RV32I %s
+# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck --check-prefix=RV64I %s
+--- |
+
+ @x = global i32 0, align 4
+
+ define ptr @global_addr() {
+ entry:
+ ret ptr @x
+ }
+
+...
+---
+name: global_addr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb, preferred-register: '' }
+body: |
+ bb.1.entry:
+ ; RV32I-LABEL: name: global_addr
+ ; RV32I: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) @x
+ ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], target-flags(riscv-lo) @x
+ ; RV32I-NEXT: $x10 = COPY [[ADDI]]
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV64I-LABEL: name: global_addr
+ ; RV64I: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) @x
+ ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], target-flags(riscv-lo) @x
+ ; RV64I-NEXT: $x10 = COPY [[ADDI]]
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = G_GLOBAL_VALUE @x
+ $x10 = COPY %0(p0)
+ PseudoRET implicit $x10
+
+...
>From b1f7484e6ca571121ffeffd28316b48e6befb59c Mon Sep 17 00:00:00 2001
From: Nitin John Raj <nitin.raj at sifive.com>
Date: Fri, 6 Oct 2023 13:25:21 -0700
Subject: [PATCH 4/4] Rename test to reflect that rv32 and rv64 tests are in
the same file
---
.../{global-value-rv32.mir => global-value.mir} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/{global-value-rv32.mir => global-value.mir} (100%)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/global-value-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/global-value.mir
similarity index 100%
rename from llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/global-value-rv32.mir
rename to llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/global-value.mir
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