[llvm] [RISCV] Strip W suffix from ADDIW, SRLIW, and SRAIW (PR #68425)

Fri Oct 6 09:40:07 PDT 2023

topperc wrote:

> > I don't think it's safe to do this for SRAIW and SRLIW. SRAIW copies bit 31 to all the shifted right bits, SRAI copies bit 63. SRLIW inserts zeros starting at bit 31, SRLI starts at bit 63.
> 
> Are you sure about this semantic? The wording from the specification simple says "SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. SLLIW, SRLIW, and SRAIW encodings with imm[5] ̸= 0 are reserved." I wouldn't get your stated semantic from this without some very tortured reading of "operated on 32-bit values".
> 
> Assuming you're correct about the semantic, I definitely agree these are unsound and need removed.

I'm pretty sure. These are our isel patterns for them. Which are we get from type legalization of i32 lshr/ashr.

def : Pat<(i64 (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt)),
          (SRLIW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
          (SRAIW GPR:$rs1, uimm5:$shamt)>;

https://github.com/llvm/llvm-project/pull/68425