[llvm] 98b114d - [InstCombine] Retain exact instruction name for some cases in SimplifyDemandedUseBits. (#68371)
via llvm-commits
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Fri Oct 6 09:11:39 PDT 2023
Author: Craig Topper
Date: 2023-10-06T09:11:36-07:00
New Revision: 98b114d1c707d5981244d44d747a17413ffab12b
URL: https://github.com/llvm/llvm-project/commit/98b114d1c707d5981244d44d747a17413ffab12b
DIFF: https://github.com/llvm/llvm-project/commit/98b114d1c707d5981244d44d747a17413ffab12b.diff
LOG: [InstCombine] Retain exact instruction name for some cases in SimplifyDemandedUseBits. (#68371)
Retain name for SExt->ZExt and AShr->LShr. Previously SExt->ZExt copied
the name with a numeric suffix. AShr->LShr dropped it.
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index abdaf167d3d9dfb..5b5d2da041f1447 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -461,7 +461,8 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
if (InputKnown.isNonNegative() ||
DemandedMask.getActiveBits() <= SrcBitWidth) {
// Convert to ZExt cast.
- CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName());
+ CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy);
+ NewCast->takeName(I);
return InsertNewInstWith(NewCast, I->getIterator());
}
@@ -770,6 +771,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
BinaryOperator *LShr = BinaryOperator::CreateLShr(I->getOperand(0),
I->getOperand(1));
LShr->setIsExact(cast<BinaryOperator>(I)->isExact());
+ LShr->takeName(I);
return InsertNewInstWith(LShr, I->getIterator());
} else if (Known.One[BitWidth-ShiftAmt-1]) { // New bits are known one.
Known.One |= HighBits;
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