[llvm] 092ef55 - [AArch64] Fix for misched-branch-targets.mir test

[via llvm-commits]

Author: Anatoly Trosinenko
Date: 2023-10-06T18:58:11+03:00
New Revision: 092ef55a564ad2ed96f4767902eaa1349ba5644d

URL: https://github.com/llvm/llvm-project/commit/092ef55a564ad2ed96f4767902eaa1349ba5644d
DIFF: https://github.com/llvm/llvm-project/commit/092ef55a564ad2ed96f4767902eaa1349ba5644d.diff

LOG: [AArch64] Fix for misched-branch-targets.mir test

Fix test failure in non-assertion builds introduced by
f1b2dd2a111f038420b3f69d4ce0b3b3f245c873.

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/misched-branch-targets.mir

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AArch64/misched-branch-targets.mir b/llvm/test/CodeGen/AArch64/misched-branch-targets.mir
index f32c1e964f97356..40f148438e537d2 100644
--- a/llvm/test/CodeGen/AArch64/misched-branch-targets.mir
+++ b/llvm/test/CodeGen/AArch64/misched-branch-targets.mir
@@ -1,6 +1,9 @@
 # RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck %s
 # RUN: llc -o - -run-pass=postmisched %s | FileCheck %s
 
+# REQUIRES: asserts
+# -misched=shuffle is only available with assertions enabled
+
 # Check that instructions that are recognized as branch targets by BTI
 # are not reordered by machine instruction schedulers.