[llvm] [AMDGPU][CodeGen] Update support (soffset + offset) s_buffer_load's (PR #68302)

[via llvm-commits]

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@@ -33,6 +33,11 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
 
   int64_t Offset;
   if (Def->getOpcode() == TargetOpcode::G_ADD) {
+    // A 32-bit (address + offset) should not cause unsigned 32-bit integer
+    // wraparound, because s_load instructions perform the addition in 64 bits.
+    if (!Def->getFlag(MachineInstr::NoUWrap) &&
+        MRI.getType(Reg).getScalarSizeInBits() == 32 && checkNUW)
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Acim-Maravic wrote:

I do not think that there is case where Reg is not 32-bit register. I can make test for that...

https://github.com/llvm/llvm-project/pull/68302