[llvm] [AMDGPU][GlobalIsel] Introduce isRegType to check for legal types, instead of checking bit width. (PR #68189)

[via llvm-commits]

================
@@ -272,6 +272,104 @@ static LegalityPredicate elementTypeIsLegal(unsigned TypeIdx) {
   };
 }
 
+static const LLT S1 = LLT::scalar(1);
+static const LLT S8 = LLT::scalar(8);
+static const LLT S16 = LLT::scalar(16);
+static const LLT S32 = LLT::scalar(32);
+static const LLT S64 = LLT::scalar(64);
+static const LLT S96 = LLT::scalar(96);
+static const LLT S128 = LLT::scalar(128);
+static const LLT S160 = LLT::scalar(160);
+static const LLT S224 = LLT::scalar(224);
+static const LLT S256 = LLT::scalar(256);
+static const LLT S512 = LLT::scalar(512);
+static const LLT MaxScalar = LLT::scalar(MaxRegisterSize);
+
+static const LLT V2S8 = LLT::fixed_vector(2, 8);
+static const LLT V2S16 = LLT::fixed_vector(2, 16);
+static const LLT V4S16 = LLT::fixed_vector(4, 16);
+static const LLT V6S16 = LLT::fixed_vector(6, 16);
+static const LLT V8S16 = LLT::fixed_vector(8, 16);
+static const LLT V10S16 = LLT::fixed_vector(10, 16);
+static const LLT V12S16 = LLT::fixed_vector(12, 16);
+static const LLT V16S16 = LLT::fixed_vector(16, 16);
+
+static const LLT V2S32 = LLT::fixed_vector(2, 32);
+static const LLT V3S32 = LLT::fixed_vector(3, 32);
+static const LLT V4S32 = LLT::fixed_vector(4, 32);
+static const LLT V5S32 = LLT::fixed_vector(5, 32);
+static const LLT V6S32 = LLT::fixed_vector(6, 32);
+static const LLT V7S32 = LLT::fixed_vector(7, 32);
+static const LLT V8S32 = LLT::fixed_vector(8, 32);
+static const LLT V9S32 = LLT::fixed_vector(9, 32);
+static const LLT V10S32 = LLT::fixed_vector(10, 32);
+static const LLT V11S32 = LLT::fixed_vector(11, 32);
+static const LLT V12S32 = LLT::fixed_vector(12, 32);
+static const LLT V16S32 = LLT::fixed_vector(16, 32);
+static const LLT V32S32 = LLT::fixed_vector(32, 32);
+
+static const LLT V2S64 = LLT::fixed_vector(2, 64);
+static const LLT V3S64 = LLT::fixed_vector(3, 64);
+static const LLT V4S64 = LLT::fixed_vector(4, 64);
+static const LLT V5S64 = LLT::fixed_vector(5, 64);
+static const LLT V6S64 = LLT::fixed_vector(6, 64);
+static const LLT V7S64 = LLT::fixed_vector(7, 64);
+static const LLT V8S64 = LLT::fixed_vector(8, 64);
+static const LLT V16S64 = LLT::fixed_vector(16, 64);
+
+static const LLT V2S128 = LLT::fixed_vector(2, 128);
+static const LLT V4S128 = LLT::fixed_vector(4, 128);
+
+static std::initializer_list<LLT> AllScalarTypes = {S32,  S64,  S96,  S128,
+                                                    S160, S224, S256, S512};
+
+static std::initializer_list<LLT> AllS16Vectors{
+    V2S16, V4S16, V6S16, V8S16, V10S16, V12S16, V16S16, V2S128, V4S128};
+
+static std::initializer_list<LLT> AllS32Vectors = {
+    V2S32, V3S32,  V4S32,  V5S32,  V6S32,  V7S32, V8S32,
+    V9S32, V10S32, V11S32, V12S32, V16S32, V32S32};
+
+static std::initializer_list<LLT> AllS64Vectors = {V2S64, V3S64, V4S64, V5S64,
+                                                   V6S64, V7S64, V8S64, V16S64};
+
+static bool typeInSet(LLT Ty, std::initializer_list<LLT> TypesInit) {
+  SmallVector<LLT, 4> Types = TypesInit;
+  return llvm::is_contained(Types, Ty);
+}
+
+static LLT GetAddrSpacePtr(unsigned AS, const GCNTargetMachine &TM) {
+  return LLT::pointer(AS, TM.getPointerSizeInBits(AS));
+}
+
+static bool isRegType(LLT Ty, const GCNTargetMachine &TM) {
+  const LLT GlobalPtr = GetAddrSpacePtr(AMDGPUAS::GLOBAL_ADDRESS, TM);
+  const LLT LocalPtr = GetAddrSpacePtr(AMDGPUAS::LOCAL_ADDRESS, TM);
+  const LLT FlatPtr = GetAddrSpacePtr(AMDGPUAS::FLAT_ADDRESS, TM);
+
+  // TODO: list all possible ptr vectors
+  const LLT V2FlatPtr = LLT::fixed_vector(2, FlatPtr);
+  const LLT V3LocalPtr = LLT::fixed_vector(3, LocalPtr);
+  const LLT V5LocalPtr = LLT::fixed_vector(5, LocalPtr);
+  const LLT V16LocalPtr = LLT::fixed_vector(16, LocalPtr);
+  const LLT V2GlobalPtr = LLT::fixed_vector(2, GlobalPtr);
+  const LLT V4GlobalPtr = LLT::fixed_vector(4, GlobalPtr);
+
+  std::initializer_list<LLT> AllPtrTypes{V2FlatPtr,   V3LocalPtr,  V5LocalPtr,
+                                         V16LocalPtr, V2GlobalPtr, V4GlobalPtr};
+
+  return typeInSet(Ty, AllS32Vectors) || typeInSet(Ty, AllS64Vectors) ||
+         typeInSet(Ty, AllScalarTypes) || typeInSet(Ty, AllS16Vectors) ||
+         typeInSet(Ty, AllPtrTypes) || Ty.isPointer();
+}
+
+static LegalityPredicate isRegType(unsigned TypeIdx,
----------------
sstipanovic wrote:

isRegisterType check is not sufficient. For example it considers v13s32 as legal which doesn't have corresponding reg class. If this approach is accepted, this would be the first step to replace isRegisterType with isRegType (we can name it differently, of course). The idea is to replace it step by step because it is not as straight forward as replacing all calls to isRegisterType with isRegType.

https://github.com/llvm/llvm-project/pull/68189