[llvm] [AMDGPU] Use correct operand order for shifts (PR #68299)

[via llvm-commits]

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@@ -2432,10 +2432,13 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
         if (Offset == 0) {
           unsigned OpCode = IsSALU && !LiveSCC ? AMDGPU::S_LSHR_B32
                                                : AMDGPU::V_LSHRREV_B32_e64;
-          // XXX - This never happens because of emergency scavenging slot at 0?
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rovka wrote:

Yep, I hit this in an OpenMP test after a [change to FixSGPRCopies](https://github.com/llvm/llvm-project/pull/66882).

https://github.com/llvm/llvm-project/pull/68299