[llvm] [RISCV][GlobalISel] Select G_GLOBAL_VALUE (PR #68380)

via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 5 21:31:56 PDT 2023


github-actions[bot] wrote:


<!--LLVM CODE FORMAT COMMENT: {clang-format}-->

:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff da0ce32cc3221686f30a6267f43d8c5dd469ef80 c46b680333e205315569a865dcfcf549a29b62fa -- llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 669a19df0939..1619702b99f4 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -98,7 +98,8 @@ private:
 RISCVInstructionSelector::RISCVInstructionSelector(
     const RISCVTargetMachine &TM, const RISCVSubtarget &STI,
     const RISCVRegisterBankInfo &RBI)
-    : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM),
+    : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI),
+      TM(TM),
 
 #define GET_GLOBALISEL_PREDICATES_INIT
 #include "RISCVGenGlobalISel.inc"
@@ -282,16 +283,16 @@ bool RISCVInstructionSelector::preISelLower(MachineInstr &MI,
     switch (TM.getCodeModel()) {
     case CodeModel::Small: {
       const GlobalValue *GV = MI.getOperand(1).getGlobal();
-      MachineInstr *Result = MIB.buildInstr(RISCV::G_HI)
-        .addGlobalAddress(GV, 0, RISCVII::MO_HI);
+      MachineInstr *Result =
+          MIB.buildInstr(RISCV::G_HI).addGlobalAddress(GV, 0, RISCVII::MO_HI);
 
       if (!constrainSelectedInstRegOperands(*Result, TII, TRI, RBI))
         return false;
 
       Register AddrHiReg = Result.getOperand(0).getReg();
       Result = MIB.buildInstr(RISCV::G_ADD_LO)
-        .addReg(AddrHiReg)
-        .addGlobalAddress(GV, 0, RISCVII::MO_LO);
+                   .addReg(AddrHiReg)
+                   .addGlobalAddress(GV, 0, RISCVII::MO_LO);
 
       if (!constrainSelectedInstRegOperands(*Result, TII, TRI, RBI))
         return false;

``````````

</details>


https://github.com/llvm/llvm-project/pull/68380


More information about the llvm-commits mailing list