[llvm] [AMDGPU] Use absolute relocations when compiling for AMDPAL and Mesa3D (PR #67791)

[Nicolai Hähnle via llvm-commits]

================
@@ -2762,7 +2766,60 @@ bool AMDGPULegalizerInfo::buildPCRelGlobalAddress(Register DstReg, LLT PtrTy,
   if (PtrTy.getSizeInBits() == 32)
     B.buildExtract(DstReg, PCReg, 0);
   return true;
- }
+}
+
+// Emit a ABS32_LO / ABS32_HI relocation stub.
+void AMDGPULegalizerInfo::buildAbsGlobalAddress(
+    Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
+    MachineRegisterInfo &MRI) const {
+  bool RequiresHighHalf = PtrTy.getSizeInBits() != 32;
+
+  LLT S32 = LLT::scalar(32);
+
+  // In case we don't need the upper half, write directly to the dest reg.
+  Register AddrLo;
+
+  if (!RequiresHighHalf) {
+    AddrLo = DstReg;
+  } else {
+    assert(PtrTy.getSizeInBits() == 64 &&
+           "Must provide a 64-bit pointer type!");
+
+    AddrLo = MRI.createGenericVirtualRegister(S32);
+  }
+
+  if (!MRI.getRegClassOrNull(AddrLo))
+    MRI.setRegClass(AddrLo, &AMDGPU::SReg_32RegClass);
+
+  // Write the lower half.
+  B.buildInstr(AMDGPU::S_MOV_B32)
+      .addDef(AddrLo)
+      .addGlobalAddress(GV, 0, SIInstrInfo::MO_ABS32_LO);
----------------
nhaehnle wrote:

This change doesn't actually address the concern: if DstReg is assigned a vector register class for some reason, then this creates an S_MOV_B32 with a vector destination, which is illegal and not a great look.

FWIW, I think that's a big part of the reason for why a lot of the GlobalISel code tends to err on the side of creating COPYs.

https://github.com/llvm/llvm-project/pull/67791