[llvm] [RISCV] Support Xsfvfwmaccqqq extensions (PR #68296)

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git-clang-format --diff 3a35ca01fc55f27315d1652ec1dedff10e79918b fc484770303cf50819e09dafd0f4f00760e67e3c -- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vfwmacc_4x4x4.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vfwmacc_4x4x4.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vfwmacc_4x4x4.c clang/include/clang/Support/RISCVVIntrinsicUtils.h clang/lib/Sema/SemaRISCVVectorLookup.cpp clang/test/Sema/rvv-required-features-invalid.c clang/test/Sema/rvv-required-features.c clang/utils/TableGen/RISCVVEmitter.cpp llvm/lib/Support/RISCVISAInfo.cpp llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/unittests/Support/RISCVISAInfoTest.cpp
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diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 33f654b26884..b6b3c4ae4bbb 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -558,8 +558,9 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
                           "XTHeadVdot custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
                           "SiFive VCIX custom opcode table");
-    TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
-                          "SiFive Matrix Multiplication Instruction opcode table");
+    TRY_TO_DECODE_FEATURE(
+        RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
+        "SiFive Matrix Multiplication Instruction opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32,
                           "Sifive CIE custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index cf344b786fb5..1a029b87135a 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -630,7 +630,7 @@ TEST(getTargetFeatureForExtension, RetrieveTargetFeatureFromOneExt) {
 
 TEST(RiscvExtensionsHelp, CheckExtensions) {
   std::string ExpectedOutput =
-R"(All available -march extensions for RISC-V
+      R"(All available -march extensions for RISC-V
 
     Name                Version   Description
     i                   2.1       This is a long dummy description

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https://github.com/llvm/llvm-project/pull/68296