[PATCH] D141060: [opt] Infer DataLayout from triple if not specified
Alexander Richardson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 4 11:28:40 PDT 2023
arichardson added a subscriber: arsenm.
arichardson added a comment.
CC: @arsenm for non-obvious AMDGPU test diffs
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Comment at: llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.defined.nobuiltin.ll:59
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[__SINCOS_:%.*]] = alloca float, align 4
-; CHECK-NEXT: [[TMP0:%.*]] = call contract float @_Z6sincosfPU3AS0f(float [[X]], ptr [[__SINCOS_]])
-; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[__SINCOS_]], align 4
-; CHECK-NEXT: store float [[TMP0]], ptr addrspace(1) [[SIN_OUT]], align 4
+; CHECK-NEXT: [[__SINCOS_:%.*]] = alloca float, align 4, addrspace(5)
+; CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr addrspace(5) [[__SINCOS_]] to ptr
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This seems correct since it's now allocating in the alloca AS, but would be good to get a confirmation here.
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Comment at: llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll:487
; CHECK-LABEL: define {{[^@]+}}@void_one_out_arg_i32_1_use
-; CHECK-SAME: (ptr [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] {
-; CHECK-NEXT: [[TMP2:%.*]] = call [[VOID_ONE_OUT_ARG_I32_1_USE:%.*]] @void_one_out_arg_i32_1_use.body(ptr poison)
-; CHECK-NEXT: [[TMP3:%.*]] = extractvalue [[VOID_ONE_OUT_ARG_I32_1_USE]] [[TMP2]], 0
-; CHECK-NEXT: store i32 [[TMP3]], ptr [[TMP0]], align 4
+; CHECK-SAME: (ptr [[VAL:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: store i32 0, ptr [[VAL]], align 4
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I'm not quite sure what is going on in this test, it seems like the correct datalayout is causing a huge difference.
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Comment at: llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1.ll:50
; CHECK-ALU64-NEXT: .Ltmp7:
-; CHECK-ALU64-NEXT: r1 = 50
+; CHECK-ALU64-NEXT: r1 = 18
; CHECK-ALU64-NEXT: .loc 1 13 67 # test.c:13:67
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Not quite sure what is going here would be good to get a second opinion.
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Comment at: llvm/test/Instrumentation/SanitizerCoverage/cmp-tracing-api-x86_32.ll:9
; CHECK-NEXT: entry:
-; CHECK-NEXT: call void @__sanitizer_cov_trace_pc_guard(ptr @__sancov_gen_) #[[ATTR1:[0-9]+]]
+; CHECK-NEXT: call void @__sanitizer_cov_trace_pc_guard(ptr inttoptr (i32 ptrtoint (ptr @__sancov_gen_ to i32) to ptr)) #[[ATTR1:[0-9]+]]
; CHECK-NEXT: ret i32 0
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This is rather odd, sounds like we are introducing a unnecessary ptrtoint/inttoptr pair.
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Comment at: llvm/test/Instrumentation/SanitizerCoverage/cmp-tracing-api-x86_32.ll:16
-; CHECK-DAG: declare void @__sanitizer_cov_trace_pc_indir(i64)
+; CHECK-DAG: declare void @__sanitizer_cov_trace_pc_indir(i32)
; CHECK-DAG: declare void @__sanitizer_cov_trace_cmp1(i8 zeroext, i8 zeroext)
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This looks correct to me but worth double-checking.
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Comment at: llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll:31
+;
+; R600-LABEL: @test_atomicrmw_xchg_i8_global_agent(
+; R600-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i32(ptr addrspace(1) [[PTR:%.*]], i32 -4)
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i32 vs i64 change so I had to use a different prefix
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Comment at: llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll:36
; PWR7-NEXT: store i128 [[DESIRE:%.*]], ptr [[TMP0]], align 8
-; PWR7-NEXT: [[TMP1:%.*]] = alloca i128, align 8
-; PWR7-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[TMP1]])
-; PWR7-NEXT: store i128 [[NEW:%.*]], ptr [[TMP1]], align 8
-; PWR7-NEXT: [[TMP2:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, ptr [[ADDR:%.*]], ptr [[TMP0]], ptr [[TMP1]], i32 5, i32 5)
-; PWR7-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[TMP1]])
-; PWR7-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP0]], align 8
+; PWR7-NEXT: [[TMP1:%.*]] = call zeroext i1 @__atomic_compare_exchange_16(ptr [[ADDR:%.*]], ptr [[TMP0]], i128 [[NEW:%.*]], i32 5, i32 5)
+; PWR7-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8
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Looks like the correct data layout means we now call the optimized libcall here?
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Comment at: llvm/test/Transforms/CodeGenPrepare/AMDGPU/sink-addrspacecast.ll:128
; CHECK-SAME: i1 [[PRED:%.*]], ptr [[PTR:%.*]]) {
+; CHECK-NEXT: [[PTR_CAST:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(3)
; CHECK-NEXT: br i1 [[PRED]], label [[L1:%.*]], label [[L2:%.*]]
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I have no idea why this one is no longer being sunk.
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Comment at: llvm/test/Transforms/CodeGenPrepare/AMDGPU/sink-addrspacecast.ll:152
; CHECK-SAME: i1 [[PRED:%.*]], ptr [[PTR:%.*]]) {
+; CHECK-NEXT: [[PTR_CAST:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(5)
; CHECK-NEXT: br i1 [[PRED]], label [[L1:%.*]], label [[L2:%.*]]
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Same here.
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Comment at: llvm/test/Transforms/InferFunctionAttrs/annotate.ll:5
; RUN: opt < %s -mtriple=nvptx -passes=inferattrs -S | FileCheck --match-full-lines --check-prefixes=CHECK-NOLINUX,CHECK-NVPTX %s
-; RUN: opt < %s -mtriple=powerpc-ibm-aix-xcoff -passes=inferattrs -S | FileCheck --match-full-lines --check-prefixes=CHECK-AIX %s
+; RUN: opt < %s -mtriple=powerpc64-ibm-aix-xcoff -passes=inferattrs -S | FileCheck --match-full-lines --check-prefixes=CHECK-NOLINUX,CHECK-AIX %s
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Had to change this to ppc64 since the function signatures only work for 64-bit systems (with a 32-bit datalayout vec_calloc is not detected as a libcall).
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Comment at: llvm/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll:6
declare i1 @foo(ptr, ptr, ptr) nounwind
; Check that redundant phi elimination ran
----------------
The diffs here look reasonable, but I'm not sure why they are happening.
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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll:80
; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK: vector.ph:
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This one might need further investigation.
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Comment at: llvm/test/Transforms/SafeStack/X86/setjmp2.ll:3
+; RUN: opt -safe-stack -S -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=I386
+; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s --check-prefix=X86-64
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Had to split this into two due to changed alignment.
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https://reviews.llvm.org/D141060/new/
https://reviews.llvm.org/D141060
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