[llvm] [X86] Add missed type extension and truncation during combine (PR #67168)
Evgenii Kudriashov via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 4 08:32:02 PDT 2023
https://github.com/e-kud updated https://github.com/llvm/llvm-project/pull/67168
>From ba11cc2a59c45389974aa4af63a71530332562f0 Mon Sep 17 00:00:00 2001
From: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: Thu, 21 Sep 2023 10:03:09 -0700
Subject: [PATCH] [X86] Add missed type extension and truncation during combine
Type extension and truncation is missed when combining loads and stores
for ptr32 and ptr64.
Closes #66873
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 13 +++++++------
llvm/test/CodeGen/X86/mixed-ptr-sizes.ll | 21 +++++++++++++++------
2 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c4cd2a672fe7b26..9b2e61f0d2a48f9 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -49820,9 +49820,9 @@ static SDValue combineLoad(SDNode *N, SelectionDAG &DAG,
if (PtrVT != Ld->getBasePtr().getSimpleValueType()) {
SDValue Cast =
DAG.getAddrSpaceCast(dl, PtrVT, Ld->getBasePtr(), AddrSpace, 0);
- return DAG.getLoad(RegVT, dl, Ld->getChain(), Cast, Ld->getPointerInfo(),
- Ld->getOriginalAlign(),
- Ld->getMemOperand()->getFlags());
+ return DAG.getExtLoad(Ext, dl, RegVT, Ld->getChain(), Cast,
+ Ld->getPointerInfo(), MemVT, Ld->getOriginalAlign(),
+ Ld->getMemOperand()->getFlags());
}
}
@@ -50324,9 +50324,10 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
if (PtrVT != St->getBasePtr().getSimpleValueType()) {
SDValue Cast =
DAG.getAddrSpaceCast(dl, PtrVT, St->getBasePtr(), AddrSpace, 0);
- return DAG.getStore(St->getChain(), dl, StoredVal, Cast,
- St->getPointerInfo(), St->getOriginalAlign(),
- St->getMemOperand()->getFlags(), St->getAAInfo());
+ return DAG.getTruncStore(
+ St->getChain(), dl, StoredVal, Cast, St->getPointerInfo(), StVT,
+ St->getOriginalAlign(), St->getMemOperand()->getFlags(),
+ St->getAAInfo());
}
}
diff --git a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
index 2dd6011f36b775f..67539b07f5716c1 100644
--- a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
+++ b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
@@ -261,7 +261,7 @@ define i64 @test_load_sptr32_zext_i64(ptr addrspace(270) %i) {
; CHECK-LABEL: test_load_sptr32_zext_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movslq %ecx, %rax
-; CHECK-NEXT: movq (%rax), %rax
+; CHECK-NEXT: movl (%rax), %eax
; CHECK-NEXT: retq
;
; CHECK-O0-LABEL: test_load_sptr32_zext_i64:
@@ -278,11 +278,20 @@ entry:
}
define void @test_store_sptr32_trunc_i1(ptr addrspace(270) %s, i32 %i) {
-; ALL-LABEL: test_store_sptr32_trunc_i1:
-; ALL: # %bb.0: # %entry
-; ALL-NEXT: movslq %ecx, %rax
-; ALL-NEXT: movl %edx, (%rax)
-; ALL-NEXT: retq
+; CHECK-LABEL: test_store_sptr32_trunc_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movslq %ecx, %rax
+; CHECK-NEXT: andl $1, %edx
+; CHECK-NEXT: movb %dl, (%rax)
+; CHECK-NEXT: retq
+;
+; CHECK-O0-LABEL: test_store_sptr32_trunc_i1:
+; CHECK-O0: # %bb.0: # %entry
+; CHECK-O0-NEXT: movslq %ecx, %rax
+; CHECK-O0-NEXT: andl $1, %edx
+; CHECK-O0-NEXT: movb %dl, %cl
+; CHECK-O0-NEXT: movb %cl, (%rax)
+; CHECK-O0-NEXT: retq
entry:
%0 = trunc i32 %i to i1
store i1 %0, ptr addrspace(270) %s
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