[llvm] [RISCV] Generaize reduction tree matching to all integer reductions (PR #68014)

[Luke Lau via llvm-commits]

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@@ -11126,8 +11151,15 @@ combineBinOpOfExtractToReduceTree(SDNode *N, SelectionDAG &DAG,
 
   const SDLoc DL(N);
   const EVT VT = N->getValueType(0);
-  [[maybe_unused]] const unsigned Opc = N->getOpcode();
-  assert(Opc == ISD::ADD && "extend this to other reduction types");
+
+  // TODO: Handle floating point here.
+  if (!VT.isInteger())
+    return SDValue();
+
+  const unsigned Opc = N->getOpcode();
+  const unsigned ReduceOpc = getVecReduceOpcode(Opc);
+  assert(Opc == ISD::getVecReduceBaseOpcode(ReduceOpc) &&
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lukel97 wrote:

Maybe `isOperationLegalOrCustomOrPromote(ReduceOpc, VT)`?

https://github.com/llvm/llvm-project/pull/68014