[llvm] [AMDGPU] Use absolute relocations when compiling for AMDPAL and Mesa3D (PR #67791)

[Thomas Symalla via llvm-commits]

================
@@ -2762,7 +2766,46 @@ bool AMDGPULegalizerInfo::buildPCRelGlobalAddress(Register DstReg, LLT PtrTy,
   if (PtrTy.getSizeInBits() == 32)
     B.buildExtract(DstReg, PCReg, 0);
   return true;
- }
+}
+
+// Emit a ABS32_LO / ABS32_HI relocation stub.
+void AMDGPULegalizerInfo::buildAbsGlobalAddress(
+    Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
+    int64_t Offset, MachineRegisterInfo &MRI) const {
+  bool IsDwordTy = PtrTy.getSizeInBits() == 32;
+
+  LLT S32 = LLT::scalar(32);
+
+  Register AddrDst;
+  if (IsDwordTy) {
+    AddrDst = MRI.createGenericVirtualRegister(S32);
+    MRI.setRegClass(AddrDst, &AMDGPU::SReg_32RegClass);
+  } else {
+    assert(PtrTy.getSizeInBits() == 64 &&
+           "Must provide a 64-bit pointer type!");
+    AddrDst = MRI.createGenericVirtualRegister(LLT::scalar(64));
+    MRI.setRegClass(AddrDst, &AMDGPU::SReg_64RegClass);
+  }
+
+  Register AddrLo = MRI.createGenericVirtualRegister(S32);
+  MRI.setRegClass(AddrLo, &AMDGPU::SReg_32RegClass);
+
+  B.buildInstr(AMDGPU::S_MOV_B32)
+      .addDef(AddrLo)
+      .addGlobalAddress(GV, 0, SIInstrInfo::MO_ABS32_LO);
+
+  if (!IsDwordTy) {
+    Register AddrHi = MRI.createGenericVirtualRegister(S32);
+    MRI.setRegClass(AddrHi, &AMDGPU::SReg_32RegClass);
+    B.buildInstr(AMDGPU::S_MOV_B32)
+        .addDef(AddrHi)
+        .addGlobalAddress(GV, 0, SIInstrInfo::MO_ABS32_HI);
+
----------------
tsymalla wrote:

I think the solution I provide works without a separate AddrDst register, and can write directly to the DstReg, if appropriate, and merges otherwise

https://github.com/llvm/llvm-project/pull/67791