[llvm] d97f49b - [X86] Add pointer mask test coverage for implicit NSW/NUW adds
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 3 09:33:07 PDT 2023
Author: Simon Pilgrim
Date: 2023-10-03T17:32:28+01:00
New Revision: d97f49b7e0be80af575d7156057e1e57ab71440c
URL: https://github.com/llvm/llvm-project/commit/d97f49b7e0be80af575d7156057e1e57ab71440c
DIFF: https://github.com/llvm/llvm-project/commit/d97f49b7e0be80af575d7156057e1e57ab71440c.diff
LOG: [X86] Add pointer mask test coverage for implicit NSW/NUW adds
promoteExtBeforeAdd currently relies on a NSW/NUW flag, which have been lost by previous folds.
Added:
Modified:
llvm/test/CodeGen/X86/addr-mode-matcher-3.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/addr-mode-matcher-3.ll b/llvm/test/CodeGen/X86/addr-mode-matcher-3.ll
index 37d76ffb646f08a..9896b745187aadd 100644
--- a/llvm/test/CodeGen/X86/addr-mode-matcher-3.ll
+++ b/llvm/test/CodeGen/X86/addr-mode-matcher-3.ll
@@ -2,8 +2,55 @@
; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
-define i32 @mask_offset_scale_i32_i64(ptr %base, i32 %i) {
-; X86-LABEL: mask_offset_scale_i32_i64:
+define i32 @mask_add_sext_i32_i64(ptr %base, i32 %i) {
+; X86-LABEL: mask_add_sext_i32_i64:
+; X86: # %bb.0:
+; X86-NEXT: movsbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl 12(%ecx,%eax,4), %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: mask_add_sext_i32_i64:
+; X64: # %bb.0:
+; X64-NEXT: sarl $24, %esi
+; X64-NEXT: addl $3, %esi
+; X64-NEXT: movslq %esi, %rax
+; X64-NEXT: movl (%rdi,%rax,4), %eax
+; X64-NEXT: retq
+ %mask = ashr i32 %i, 24
+ %offset = add i32 %mask, 3
+ %sext = sext i32 %offset to i64
+ %gep = getelementptr i32, ptr %base, i64 %sext
+ %ret = load i32, ptr %gep
+ ret i32 %ret
+}
+
+define i32 @mask_add_zext_i32_i64(ptr %base, i32 %i) {
+; X86-LABEL: mask_add_zext_i32_i64:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: andl $15, %ecx
+; X86-NEXT: movl 12(%eax,%ecx,4), %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: mask_add_zext_i32_i64:
+; X64: # %bb.0:
+; X64-NEXT: # kill: def $esi killed $esi def $rsi
+; X64-NEXT: andl $15, %esi
+; X64-NEXT: addl $3, %esi
+; X64-NEXT: movl (%rdi,%rsi,4), %eax
+; X64-NEXT: retq
+ %mask = and i32 %i, 15
+ %offset = add i32 %mask, 3
+ %zext = zext i32 %offset to i64
+ %gep = getelementptr i32, ptr %base, i64 %zext
+ %ret = load i32, ptr %gep
+ ret i32 %ret
+}
+
+define i32 @mask_offset_scale_zext_i32_i64(ptr %base, i32 %i) {
+; X86-LABEL: mask_offset_scale_zext_i32_i64:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
@@ -11,7 +58,7 @@ define i32 @mask_offset_scale_i32_i64(ptr %base, i32 %i) {
; X86-NEXT: movl 48(%eax,%ecx), %eax
; X86-NEXT: retl
;
-; X64-LABEL: mask_offset_scale_i32_i64:
+; X64-LABEL: mask_offset_scale_zext_i32_i64:
; X64: # %bb.0:
; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: andl $65280, %esi # imm = 0xFF00
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