[llvm] e577e70 - [RISCV] Move vector pseudo hasAllNBitUsers switch into RISCVInstrInfo. NFC (#67593)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 3 04:24:16 PDT 2023
Author: Luke Lau
Date: 2023-10-03T12:24:11+01:00
New Revision: e577e7025d33ca1164206f1ccc5e20adbdbe7de6
URL: https://github.com/llvm/llvm-project/commit/e577e7025d33ca1164206f1ccc5e20adbdbe7de6
DIFF: https://github.com/llvm/llvm-project/commit/e577e7025d33ca1164206f1ccc5e20adbdbe7de6.diff
LOG: [RISCV] Move vector pseudo hasAllNBitUsers switch into RISCVInstrInfo. NFC (#67593)
The handling for vector pseudos in hasAllNBitUsers is duplicated across
RISCVISelDAGToDAG and RISCVOptWInstrs. This deduplicates it between the
two,
with the common denominator between the two call sites being the opcode
and
SEW: We need to handle extracting these separately since one operates at
the
SelectionDAG level and the other at the MachineInstr level.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 16faaa8eeb6bc63..9bf1e12584aee39 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2779,120 +2779,9 @@ static bool vectorPseudoHasAllNBitUsers(SDNode *User, unsigned UserOpNo,
if (UserOpNo == VLIdx)
return false;
- // TODO: Handle Zvbb instructions
- switch (PseudoInfo->BaseInstr) {
- default:
- return false;
-
- // 11.6. Vector Single-Width Shift Instructions
- case RISCV::VSLL_VX:
- case RISCV::VSRL_VX:
- case RISCV::VSRA_VX:
- // 12.4. Vector Single-Width Scaling Shift Instructions
- case RISCV::VSSRL_VX:
- case RISCV::VSSRA_VX:
- // Only the low lg2(SEW) bits of the shift-amount value are used.
- if (Bits < Log2SEW)
- return false;
- break;
-
- // 11.7 Vector Narrowing Integer Right Shift Instructions
- case RISCV::VNSRL_WX:
- case RISCV::VNSRA_WX:
- // 12.5. Vector Narrowing Fixed-Point Clip Instructions
- case RISCV::VNCLIPU_WX:
- case RISCV::VNCLIP_WX:
- // Only the low lg2(2*SEW) bits of the shift-amount value are used.
- if (Bits < Log2SEW + 1)
- return false;
- break;
-
- // 11.1. Vector Single-Width Integer Add and Subtract
- case RISCV::VADD_VX:
- case RISCV::VSUB_VX:
- case RISCV::VRSUB_VX:
- // 11.2. Vector Widening Integer Add/Subtract
- case RISCV::VWADDU_VX:
- case RISCV::VWSUBU_VX:
- case RISCV::VWADD_VX:
- case RISCV::VWSUB_VX:
- case RISCV::VWADDU_WX:
- case RISCV::VWSUBU_WX:
- case RISCV::VWADD_WX:
- case RISCV::VWSUB_WX:
- // 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
- case RISCV::VADC_VXM:
- case RISCV::VADC_VIM:
- case RISCV::VMADC_VXM:
- case RISCV::VMADC_VIM:
- case RISCV::VMADC_VX:
- case RISCV::VSBC_VXM:
- case RISCV::VMSBC_VXM:
- case RISCV::VMSBC_VX:
- // 11.5 Vector Bitwise Logical Instructions
- case RISCV::VAND_VX:
- case RISCV::VOR_VX:
- case RISCV::VXOR_VX:
- // 11.8. Vector Integer Compare Instructions
- case RISCV::VMSEQ_VX:
- case RISCV::VMSNE_VX:
- case RISCV::VMSLTU_VX:
- case RISCV::VMSLT_VX:
- case RISCV::VMSLEU_VX:
- case RISCV::VMSLE_VX:
- case RISCV::VMSGTU_VX:
- case RISCV::VMSGT_VX:
- // 11.9. Vector Integer Min/Max Instructions
- case RISCV::VMINU_VX:
- case RISCV::VMIN_VX:
- case RISCV::VMAXU_VX:
- case RISCV::VMAX_VX:
- // 11.10. Vector Single-Width Integer Multiply Instructions
- case RISCV::VMUL_VX:
- case RISCV::VMULH_VX:
- case RISCV::VMULHU_VX:
- case RISCV::VMULHSU_VX:
- // 11.11. Vector Integer Divide Instructions
- case RISCV::VDIVU_VX:
- case RISCV::VDIV_VX:
- case RISCV::VREMU_VX:
- case RISCV::VREM_VX:
- // 11.12. Vector Widening Integer Multiply Instructions
- case RISCV::VWMUL_VX:
- case RISCV::VWMULU_VX:
- case RISCV::VWMULSU_VX:
- // 11.13. Vector Single-Width Integer Multiply-Add Instructions
- case RISCV::VMACC_VX:
- case RISCV::VNMSAC_VX:
- case RISCV::VMADD_VX:
- case RISCV::VNMSUB_VX:
- // 11.14. Vector Widening Integer Multiply-Add Instructions
- case RISCV::VWMACCU_VX:
- case RISCV::VWMACC_VX:
- case RISCV::VWMACCSU_VX:
- case RISCV::VWMACCUS_VX:
- // 11.15. Vector Integer Merge Instructions
- case RISCV::VMERGE_VXM:
- // 11.16. Vector Integer Move Instructions
- case RISCV::VMV_V_X:
- // 12.1. Vector Single-Width Saturating Add and Subtract
- case RISCV::VSADDU_VX:
- case RISCV::VSADD_VX:
- case RISCV::VSSUBU_VX:
- case RISCV::VSSUB_VX:
- // 12.2. Vector Single-Width Averaging Add and Subtract
- case RISCV::VAADDU_VX:
- case RISCV::VAADD_VX:
- case RISCV::VASUBU_VX:
- case RISCV::VASUB_VX:
- // 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
- case RISCV::VSMUL_VX:
- // 16.1. Integer Scalar Move Instructions
- case RISCV::VMV_S_X:
- if (Bits < (1U << Log2SEW))
- return false;
- }
- return true;
+ auto NumDemandedBits =
+ RISCV::getVectorLowDemandedScalarBits(PseudoInfo->BaseInstr, Log2SEW);
+ return NumDemandedBits && Bits >= *NumDemandedBits;
}
// Return true if all users of this SDNode* only consume the lower \p Bits.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 6ee5e2d4c584049..90f7a4f1edbe947 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2847,3 +2847,115 @@ bool RISCV::hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2) {
MachineOperand FrmOp2 = MI2.getOperand(MI2FrmOpIdx);
return FrmOp1.getImm() == FrmOp2.getImm();
}
+
+std::optional<unsigned>
+RISCV::getVectorLowDemandedScalarBits(uint16_t Opcode, unsigned Log2SEW) {
+ // TODO: Handle Zvbb instructions
+ switch (Opcode) {
+ default:
+ return std::nullopt;
+
+ // 11.6. Vector Single-Width Shift Instructions
+ case RISCV::VSLL_VX:
+ case RISCV::VSRL_VX:
+ case RISCV::VSRA_VX:
+ // 12.4. Vector Single-Width Scaling Shift Instructions
+ case RISCV::VSSRL_VX:
+ case RISCV::VSSRA_VX:
+ // Only the low lg2(SEW) bits of the shift-amount value are used.
+ return Log2SEW;
+
+ // 11.7 Vector Narrowing Integer Right Shift Instructions
+ case RISCV::VNSRL_WX:
+ case RISCV::VNSRA_WX:
+ // 12.5. Vector Narrowing Fixed-Point Clip Instructions
+ case RISCV::VNCLIPU_WX:
+ case RISCV::VNCLIP_WX:
+ // Only the low lg2(2*SEW) bits of the shift-amount value are used.
+ return Log2SEW + 1;
+
+ // 11.1. Vector Single-Width Integer Add and Subtract
+ case RISCV::VADD_VX:
+ case RISCV::VSUB_VX:
+ case RISCV::VRSUB_VX:
+ // 11.2. Vector Widening Integer Add/Subtract
+ case RISCV::VWADDU_VX:
+ case RISCV::VWSUBU_VX:
+ case RISCV::VWADD_VX:
+ case RISCV::VWSUB_VX:
+ case RISCV::VWADDU_WX:
+ case RISCV::VWSUBU_WX:
+ case RISCV::VWADD_WX:
+ case RISCV::VWSUB_WX:
+ // 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
+ case RISCV::VADC_VXM:
+ case RISCV::VADC_VIM:
+ case RISCV::VMADC_VXM:
+ case RISCV::VMADC_VIM:
+ case RISCV::VMADC_VX:
+ case RISCV::VSBC_VXM:
+ case RISCV::VMSBC_VXM:
+ case RISCV::VMSBC_VX:
+ // 11.5 Vector Bitwise Logical Instructions
+ case RISCV::VAND_VX:
+ case RISCV::VOR_VX:
+ case RISCV::VXOR_VX:
+ // 11.8. Vector Integer Compare Instructions
+ case RISCV::VMSEQ_VX:
+ case RISCV::VMSNE_VX:
+ case RISCV::VMSLTU_VX:
+ case RISCV::VMSLT_VX:
+ case RISCV::VMSLEU_VX:
+ case RISCV::VMSLE_VX:
+ case RISCV::VMSGTU_VX:
+ case RISCV::VMSGT_VX:
+ // 11.9. Vector Integer Min/Max Instructions
+ case RISCV::VMINU_VX:
+ case RISCV::VMIN_VX:
+ case RISCV::VMAXU_VX:
+ case RISCV::VMAX_VX:
+ // 11.10. Vector Single-Width Integer Multiply Instructions
+ case RISCV::VMUL_VX:
+ case RISCV::VMULH_VX:
+ case RISCV::VMULHU_VX:
+ case RISCV::VMULHSU_VX:
+ // 11.11. Vector Integer Divide Instructions
+ case RISCV::VDIVU_VX:
+ case RISCV::VDIV_VX:
+ case RISCV::VREMU_VX:
+ case RISCV::VREM_VX:
+ // 11.12. Vector Widening Integer Multiply Instructions
+ case RISCV::VWMUL_VX:
+ case RISCV::VWMULU_VX:
+ case RISCV::VWMULSU_VX:
+ // 11.13. Vector Single-Width Integer Multiply-Add Instructions
+ case RISCV::VMACC_VX:
+ case RISCV::VNMSAC_VX:
+ case RISCV::VMADD_VX:
+ case RISCV::VNMSUB_VX:
+ // 11.14. Vector Widening Integer Multiply-Add Instructions
+ case RISCV::VWMACCU_VX:
+ case RISCV::VWMACC_VX:
+ case RISCV::VWMACCSU_VX:
+ case RISCV::VWMACCUS_VX:
+ // 11.15. Vector Integer Merge Instructions
+ case RISCV::VMERGE_VXM:
+ // 11.16. Vector Integer Move Instructions
+ case RISCV::VMV_V_X:
+ // 12.1. Vector Single-Width Saturating Add and Subtract
+ case RISCV::VSADDU_VX:
+ case RISCV::VSADD_VX:
+ case RISCV::VSSUBU_VX:
+ case RISCV::VSSUB_VX:
+ // 12.2. Vector Single-Width Averaging Add and Subtract
+ case RISCV::VAADDU_VX:
+ case RISCV::VAADD_VX:
+ case RISCV::VASUBU_VX:
+ case RISCV::VASUB_VX:
+ // 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
+ case RISCV::VSMUL_VX:
+ // 16.1. Integer Scalar Move Instructions
+ case RISCV::VMV_S_X:
+ return 1U << Log2SEW;
+ }
+}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 99c907a98121ae3..d56d3c0b303bf91 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -265,6 +265,12 @@ int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
// one of the instructions does not have rounding mode, false will be returned.
bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
+// If \p Opcode is a .vx vector instruction, returns the lower number of bits
+// that are used from the scalar .x operand for a given \p Log2SEW. Otherwise
+// returns null.
+std::optional<unsigned> getVectorLowDemandedScalarBits(uint16_t Opcode,
+ unsigned Log2SEW);
+
// Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
static constexpr int64_t VLMaxSentinel = -1LL;
diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 7c3eb3bdf7ea4b5..439a1bb6e1e69d2 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -88,7 +88,7 @@ static bool vectorPseudoHasAllNBitUsers(const MachineOperand &UserOp,
return false;
const MCInstrDesc &MCID = MI.getDesc();
- const uint64_t TSFlags = MI.getDesc().TSFlags;
+ const uint64_t TSFlags = MCID.TSFlags;
if (!RISCVII::hasSEWOp(TSFlags))
return false;
assert(RISCVII::hasVLOp(TSFlags));
@@ -97,120 +97,9 @@ static bool vectorPseudoHasAllNBitUsers(const MachineOperand &UserOp,
if (UserOp.getOperandNo() == RISCVII::getVLOpNum(MCID))
return false;
- // TODO: Handle Zvbb instructions
- switch (PseudoInfo->BaseInstr) {
- default:
- return false;
-
- // 11.6. Vector Single-Width Shift Instructions
- case RISCV::VSLL_VX:
- case RISCV::VSRL_VX:
- case RISCV::VSRA_VX:
- // 12.4. Vector Single-Width Scaling Shift Instructions
- case RISCV::VSSRL_VX:
- case RISCV::VSSRA_VX:
- // Only the low lg2(SEW) bits of the shift-amount value are used.
- if (Bits < Log2SEW)
- return false;
- break;
-
- // 11.7 Vector Narrowing Integer Right Shift Instructions
- case RISCV::VNSRL_WX:
- case RISCV::VNSRA_WX:
- // 12.5. Vector Narrowing Fixed-Point Clip Instructions
- case RISCV::VNCLIPU_WX:
- case RISCV::VNCLIP_WX:
- // Only the low lg2(2*SEW) bits of the shift-amount value are used.
- if (Bits < Log2SEW + 1)
- return false;
- break;
-
- // 11.1. Vector Single-Width Integer Add and Subtract
- case RISCV::VADD_VX:
- case RISCV::VSUB_VX:
- case RISCV::VRSUB_VX:
- // 11.2. Vector Widening Integer Add/Subtract
- case RISCV::VWADDU_VX:
- case RISCV::VWSUBU_VX:
- case RISCV::VWADD_VX:
- case RISCV::VWSUB_VX:
- case RISCV::VWADDU_WX:
- case RISCV::VWSUBU_WX:
- case RISCV::VWADD_WX:
- case RISCV::VWSUB_WX:
- // 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
- case RISCV::VADC_VXM:
- case RISCV::VADC_VIM:
- case RISCV::VMADC_VXM:
- case RISCV::VMADC_VIM:
- case RISCV::VMADC_VX:
- case RISCV::VSBC_VXM:
- case RISCV::VMSBC_VXM:
- case RISCV::VMSBC_VX:
- // 11.5 Vector Bitwise Logical Instructions
- case RISCV::VAND_VX:
- case RISCV::VOR_VX:
- case RISCV::VXOR_VX:
- // 11.8. Vector Integer Compare Instructions
- case RISCV::VMSEQ_VX:
- case RISCV::VMSNE_VX:
- case RISCV::VMSLTU_VX:
- case RISCV::VMSLT_VX:
- case RISCV::VMSLEU_VX:
- case RISCV::VMSLE_VX:
- case RISCV::VMSGTU_VX:
- case RISCV::VMSGT_VX:
- // 11.9. Vector Integer Min/Max Instructions
- case RISCV::VMINU_VX:
- case RISCV::VMIN_VX:
- case RISCV::VMAXU_VX:
- case RISCV::VMAX_VX:
- // 11.10. Vector Single-Width Integer Multiply Instructions
- case RISCV::VMUL_VX:
- case RISCV::VMULH_VX:
- case RISCV::VMULHU_VX:
- case RISCV::VMULHSU_VX:
- // 11.11. Vector Integer Divide Instructions
- case RISCV::VDIVU_VX:
- case RISCV::VDIV_VX:
- case RISCV::VREMU_VX:
- case RISCV::VREM_VX:
- // 11.12. Vector Widening Integer Multiply Instructions
- case RISCV::VWMUL_VX:
- case RISCV::VWMULU_VX:
- case RISCV::VWMULSU_VX:
- // 11.13. Vector Single-Width Integer Multiply-Add Instructions
- case RISCV::VMACC_VX:
- case RISCV::VNMSAC_VX:
- case RISCV::VMADD_VX:
- case RISCV::VNMSUB_VX:
- // 11.14. Vector Widening Integer Multiply-Add Instructions
- case RISCV::VWMACCU_VX:
- case RISCV::VWMACC_VX:
- case RISCV::VWMACCSU_VX:
- case RISCV::VWMACCUS_VX:
- // 11.15. Vector Integer Merge Instructions
- case RISCV::VMERGE_VXM:
- // 11.16. Vector Integer Move Instructions
- case RISCV::VMV_V_X:
- // 12.1. Vector Single-Width Saturating Add and Subtract
- case RISCV::VSADDU_VX:
- case RISCV::VSADD_VX:
- case RISCV::VSSUBU_VX:
- case RISCV::VSSUB_VX:
- // 12.2. Vector Single-Width Averaging Add and Subtract
- case RISCV::VAADDU_VX:
- case RISCV::VAADD_VX:
- case RISCV::VASUBU_VX:
- case RISCV::VASUB_VX:
- // 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
- case RISCV::VSMUL_VX:
- // 16.1. Integer Scalar Move Instructions
- case RISCV::VMV_S_X:
- if (Bits < (1U << Log2SEW))
- return false;
- }
- return true;
+ auto NumDemandedBits =
+ RISCV::getVectorLowDemandedScalarBits(PseudoInfo->BaseInstr, Log2SEW);
+ return NumDemandedBits && Bits >= *NumDemandedBits;
}
// Checks if all users only demand the lower \p OrigBits of the original
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