[llvm] [RISCV] Add sink-and-fold support for RISC-V. (PR #67602)

[Craig Topper via llvm-commits]

topperc wrote:

> @topperc Sorry for delay with the review, I was away last week. Thanks for working on this, looks great! I prefer this approach to #67024 . Have you seen any changes on spec? In my testing, this is supposed to improve mcf (but I only have the instruction count, not cycles).

I can confirm that the train dataset on 429.mcf_r went from 17766169495 instructions to 17632812468 in my local testing. I think it was `-mcpu=sifive-x280 -O3`

https://github.com/llvm/llvm-project/pull/67602