[llvm] [InstCombine] Fold comparison of adding two z/sext booleans (PR #67895)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 2 16:04:52 PDT 2023
https://github.com/elhewaty updated https://github.com/llvm/llvm-project/pull/67895
>From c06cf81ef7822a5e413878987efcadac9595abee Mon Sep 17 00:00:00 2001
From: Mohamed Atef <mohamedatef1698 at gmail.com>
Date: Sun, 1 Oct 2023 00:42:12 +0300
Subject: [PATCH 1/2] [InstCombine] Add test coverage for sext/zext boolean
additions
---
llvm/test/Transforms/InstCombine/icmp-add.ll | 1789 ++++++++++++++++++
1 file changed, 1789 insertions(+)
diff --git a/llvm/test/Transforms/InstCombine/icmp-add.ll b/llvm/test/Transforms/InstCombine/icmp-add.ll
index a2d0c3eb39d69ec..8a4b4e7448bf8a4 100644
--- a/llvm/test/Transforms/InstCombine/icmp-add.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-add.ll
@@ -5,6 +5,1795 @@ declare void @use(i32)
; PR1949
+; negative test for zext/zext additions with i16
+define i1 @cvt_icmp_0_zext_plus_zext_eq_i16(i16 %arg, i16 %arg1) {
+; CHECK-LABEL: @cvt_icmp_0_zext_plus_zext_eq_i16(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i16 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i16 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = sub nsw i32 0, [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp eq i32 [[I2]], [[I3]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i16 %arg to i32
+ %i2 = zext i16 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp eq i32 %i3, 0
+ ret i1 %i4
+}
+
+; negative test for zext/zext addtions with i8
+define i1 @cvt_icmp_0_zext_plus_zext_eq_i8(i8 %arg, i8 %arg1) {
+; CHECK-LABEL: @cvt_icmp_0_zext_plus_zext_eq_i8(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i8 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i8 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = sub nsw i32 0, [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp eq i32 [[I2]], [[I3]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i8 %arg to i32
+ %i2 = zext i8 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp eq i32 %i3, 0
+ ret i1 %i4
+}
+
+; start of positive tests
+define i1 @cvt_icmp_neg_2_zext_plus_zext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_2_zext_plus_zext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp eq i32 %i3, -2
+ ret i1 %i4
+}
+
+define i1 @cvt_icmp_neg_1_zext_plus_zext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_1_zext_plus_zext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp eq i32 %i3, -1
+ ret i1 %i4
+}
+
+define i1 @cvt_icmp_0_zext_plus_zext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_0_zext_plus_zext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp eq i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @cvt_icmp_1_zext_plus_zext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_1_zext_plus_zext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp eq i32 [[I3]], 1
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp eq i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @cvt_icmp_2_zext_plus_zext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_2_zext_plus_zext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, 2
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_neg_2_sext_plus_sext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_2_sext_plus_sext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], -2
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, -2
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_neg_1_sext_plus_sext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_1_sext_plus_sext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], -1
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, -1
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_0_sext_plus_sext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_0_sext_plus_sext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT: [[T:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, 0
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_1_sext_plus_sext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_1_sext_plus_sext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], 1
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, 1
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_2_sext_plus_sext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_2_sext_plus_sext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, 2
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_neg_2_sext_plus_zext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_2_sext_plus_zext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], -2
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, -2
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_neg_1_sext_plus_zext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_1_sext_plus_zext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], true
+; CHECK-NEXT: [[T:%.*]] = and i1 [[TMP0]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, -1
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_0_sext_plus_zext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_0_sext_plus_zext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT: [[T:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, 0
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_1_sext_plus_zext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_1_sext_plus_zext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[T:%.*]] = and i1 [[TMP0]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, 1
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_2_sext_plus_zext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_2_sext_plus_zext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, 2
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_neg_2_zext_plus_zext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_2_zext_plus_zext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 true
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ne i32 %i3, -2
+ ret i1 %i4
+}
+
+define i1 @cvt_icmp_neg_1_zext_plus_zext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_1_zext_plus_zext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 true
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ne i32 %i3, -1
+ ret i1 %i4
+}
+
+define i1 @cvt_icmp_0_zext_plus_zext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_0_zext_plus_zext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[TMP0]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ne i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @cvt_icmp_1_zext_plus_zext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_1_zext_plus_zext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp ne i32 [[I3]], 1
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ne i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @cvt_icmp_2_zext_plus_zext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_2_zext_plus_zext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, 2
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_neg_2_sext_plus_sext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_2_sext_plus_sext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], -2
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, -2
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_neg_1_sext_plus_sext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_1_sext_plus_sext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], -1
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, -1
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_0_sext_plus_sext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_0_sext_plus_sext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[TMP0]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, 0
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_1_sext_plus_sext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_1_sext_plus_sext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], 1
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, 1
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_2_sext_plus_sext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_2_sext_plus_sext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, 2
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_neg_2_sext_plus_zext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_2_sext_plus_zext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], -2
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, -2
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_neg_1_sext_plus_zext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_1_sext_plus_zext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[T:%.*]] = or i1 [[TMP0]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, -1
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_0_sext_plus_zext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_0_sext_plus_zext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[T:%.*]] = xor i1 [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, 0
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_1_sext_plus_zext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_1_sext_plus_zext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], true
+; CHECK-NEXT: [[T:%.*]] = or i1 [[TMP0]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, 1
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_2_sext_plus_zext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_2_sext_plus_zext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, 2
+ ret i1 %t
+}
+
+; test if zext i1 X + sext i1 Y converted to sext i1 X + zext i1 Y
+; and then processed
+
+define i1 @cvt_icmp_neg_2_zext_plus_sext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_2_zext_plus_sext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], -2
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, -2
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_neg_1_zext_plus_sext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_1_zext_plus_sext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[T:%.*]] = and i1 [[TMP0]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, -1
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_0_zext_plus_sext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_0_zext_plus_sext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT: [[T:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, 0
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_1_zext_plus_sext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_1_zext_plus_sext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], true
+; CHECK-NEXT: [[T:%.*]] = and i1 [[TMP0]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, 1
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_2_zext_plus_sext_eq(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_2_zext_plus_sext_eq(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp eq i32 %i3, 2
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_neg_2_zext_plus_sext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_2_zext_plus_sext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], -2
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, -2
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_neg_1_zext_plus_sext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_neg_1_zext_plus_sext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], true
+; CHECK-NEXT: [[T:%.*]] = or i1 [[TMP0]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, -1
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_0_zext_plus_sext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_0_zext_plus_sext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[T:%.*]] = xor i1 [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, 0
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_1_zext_plus_sext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_1_zext_plus_sext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[T:%.*]] = or i1 [[TMP0]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, 1
+ ret i1 %t
+}
+
+define i1 @cvt_icmp_2_zext_plus_sext_ne(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @cvt_icmp_2_zext_plus_sext_ne(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
+; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i, %i2
+ %t = icmp ne i32 %i3, 2
+ ret i1 %t
+}
+
+; test zext/zext additions with more than one use
+
+define i1 @test_cvt_icmp1(i1 %arg, i1 %arg1, ptr %p) {
+; CHECK-LABEL: @test_cvt_icmp1(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG]] to i32
+; CHECK-NEXT: store i32 [[I2]], ptr [[P:%.*]], align 4
+; CHECK-NEXT: [[I4:%.*]] = add nuw nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I4]], 1
+; CHECK-NEXT: ret i1 [[T]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg to i32
+ store i32 %i2, ptr %p
+ %i3 = load i32, ptr %p
+ %i4 = add i32 %i3, %i
+ %t = icmp eq i32 %i4, 1
+ ret i1 %t
+}
+
+define i1 @test_cvt_icmp2(i1 %arg, i1 %arg1, ptr %p) {
+; CHECK-LABEL: @test_cvt_icmp2(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: store i32 [[I2]], ptr [[P:%.*]], align 4
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg to i32
+ store i32 %i2, ptr %p
+ %i3 = load i32, ptr %p
+ %i4 = add i32 %i3, %i
+ %t = icmp eq i32 %i4, 1
+ ret i1 %t
+}
+
+; tests for ult
+define i1 @test_zext_zext_cvt_neg_2_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_neg_2_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 true
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, -2
+ ret i1 %i4
+}
+
+define i1 @test_zext_zext_cvt_neg_1_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_neg_1_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 true
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, -1
+ ret i1 %i4
+}
+
+define i1 @test_zext_zext_cvt_0_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_0_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @test_zext_zext_cvt_2_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_2_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp ult i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_sext_sext_cvt_neg_2_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_neg_2_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, -2
+ ret i1 %i4
+}
+
+define i1 @test_sext_sext_cvt_neg_1_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_neg_1_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp ne i32 [[I3]], -1
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, -1
+ ret i1 %i4
+}
+
+define i1 @test_sext_sext_cvt_0_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_0_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @test_sext_sext_cvt_1_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_1_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @test_sext_sext_cvt_2_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_2_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_sext_zext_cvt_neg_2_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_zext_cvt_neg_2_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[ARG_NOT:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG_NOT]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, -2
+ ret i1 %i4
+}
+
+define i1 @test_sext_zext_cvt_neg_1_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_zext_cvt_neg_1_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[TMP0]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, -1
+ ret i1 %i4
+}
+
+define i1 @test_sext_zext_cvt_0_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_zext_cvt_0_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @test_sext_zext_cvt_2_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_zext_cvt_2_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[ARG_NOT:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG_NOT]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_neg_1_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_neg_1_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[TMP0]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, -1
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_0_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_0_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_1_ult_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_1_ult_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, 1
+ ret i1 %i4
+}
+
+; tests for ugt
+define i1 @test_cvt_icmp4(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp4(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[TMP0]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ugt i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @test_zext_zext_cvt_neg_2_ugt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_neg_2_ugt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ugt i32 %i3, -2
+ ret i1 %i4
+}
+
+define i1 @test_zext_zext_cvt_1_ugt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_1_ugt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp ugt i32 [[I3]], 1
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ugt i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @test_zext_zext_cvt_2_ugt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_2_ugt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp eq i32 [[I3]], 3
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ugt i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_sext_sext_cvt_neg_2_ugt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_neg_2_ugt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp eq i32 [[I3]], -1
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ugt i32 %i3, -2
+ ret i1 %i4
+}
+
+define i1 @test_sext_sext_cvt_0_ugt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_0_ugt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[TMP0]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ugt i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @test_sext_sext_cvt_2_ugt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_2_ugt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp ugt i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ugt i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_neg_2_ugt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_neg_2_ugt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = and i1 [[TMP0]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ugt i32 %i3, -2
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_neg_1_ugt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_neg_1_ugt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ugt i32 %i3, -1
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_0_ugt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_0_ugt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ugt i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_1_ugt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_1_ugt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = and i1 [[TMP0]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ugt i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_2_ugt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_2_ugt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = and i1 [[TMP0]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ugt i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp5(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp5(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[TMP0]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp uge i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp6(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp6(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp ult i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ule i32 %i3, 1
+ ret i1 %i4
+}
+
+; tests for sgt
+define i1 @test_cvt_icmp7(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp7(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp ugt i32 [[I3]], 1
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sgt i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @test_zext_zext_cvt_neg_2_sgt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_neg_2_sgt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 true
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sgt i32 %i3, -2
+ ret i1 %i4
+}
+
+define i1 @test_zext_zext_cvt_neg_1_sgt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_neg_1_sgt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 true
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sgt i32 %i3, -1
+ ret i1 %i4
+}
+
+define i1 @test_zext_zext_cvt_2_sgt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_2_sgt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp eq i32 [[I3]], 3
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sgt i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_sext_sext_cvt_neg_2_sgt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_neg_2_sgt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 [[I3]], -2
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sgt i32 %i3, -2
+ ret i1 %i4
+}
+
+define i1 @test_sext_sext_cvt_0_sgt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_0_sgt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 [[I3]], 0
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sgt i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @test_sext_sext_cvt_2_sgt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_2_sgt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sgt i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_neg_2_sgt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_neg_2_sgt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 true
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sgt i32 %i3, -2
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_neg_1_sgt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_neg_1_sgt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[TMP0]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sgt i32 %i3, -1
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_0_sgt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_0_sgt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = and i1 [[TMP0]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sgt i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_1_sgt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_1_sgt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sgt i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_2_sgt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_2_sgt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sgt i32 %i3, 2
+ ret i1 %i4
+}
+
+; tests for slt
+define i1 @test_zext_zext_cvt_neg_2_slt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_neg_2_slt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp slt i32 %i3, -2
+ ret i1 %i4
+}
+
+define i1 @test_zext_zext_cvt_neg_1_slt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_neg_1_slt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp slt i32 %i3, -1
+ ret i1 %i4
+}
+
+define i1 @test_zext_zext_cvt_2_slt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_2_slt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp ult i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp slt i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_sext_sext_cvt_neg_2_slt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_neg_2_slt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp slt i32 [[I3]], -2
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp slt i32 %i3, -2
+ ret i1 %i4
+}
+
+define i1 @test_sext_sext_cvt_0_slt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_0_slt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[TMP0]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp slt i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @test_sext_sext_cvt_2_slt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_2_slt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp slt i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp slt i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_neg_2_slt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_neg_2_slt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp slt i32 %i3, -2
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_neg_1_slt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_neg_1_slt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp slt i32 %i3, -1
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_0_slt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_0_slt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = and i1 [[TMP0]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp slt i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_1_slt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_1_slt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[TMP0]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp slt i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @test_zext_sext_cvt_2_slt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_2_slt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 true
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp slt i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp8(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp8(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[TMP0]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sge i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp9(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp9(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp slt i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp10(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp10(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp ult i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sle i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp11(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp11(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp ugt i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ugt i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp12(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp12(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[TMP0]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp uge i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp13(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp13(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp14(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp14(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp ult i32 [[I3]], 3
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ule i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp15(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp15(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sgt i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp16(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp16(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 [[I3]], 1
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sge i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp17(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp17(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp slt i32 [[I3]], 2
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp slt i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp18(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp18(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp slt i32 [[I3]], 3
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sle i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp19(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp19(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = and i1 [[TMP0]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ugt i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp20(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp20(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp uge i32 %i3, 1
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp21(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp21(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[ARG_NOT:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG_NOT]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ult i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp22(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp22(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
+; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
+; CHECK-NEXT: [[I4:%.*]] = icmp ult i32 [[I3]], 3
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp ule i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp23(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp23(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sgt i32 %i3, 2
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp24(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp24(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[TMP0]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sge i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp25(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp25(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = and i1 [[TMP0]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp slt i32 %i3, 0
+ ret i1 %i4
+}
+
+define i1 @test_cvt_icmp26(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp26(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 true
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp sle i32 %i3, 1
+ ret i1 %i4
+}
+
define i1 @test1(i32 %a) {
; CHECK-LABEL: @test1(
; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A:%.*]], -5
>From 9fa7f6bccba6bf361427926a8298549da1813864 Mon Sep 17 00:00:00 2001
From: Mohamed Atef <mohamedatef1698 at gmail.com>
Date: Sun, 1 Oct 2023 01:35:26 +0300
Subject: [PATCH 2/2] [InstCombine] Fold comparison of adding two sext/zext
booleans
---
.../InstCombine/InstCombineCompares.cpp | 129 ++++----
llvm/test/Transforms/InstCombine/icmp-add.ll | 304 +++++-------------
.../test/Transforms/InstCombine/icmp-range.ll | 12 +-
3 files changed, 160 insertions(+), 285 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 9f034aba874a8c4..8e314ddd972f37a 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -26,6 +26,7 @@
#include "llvm/IR/PatternMatch.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Transforms/InstCombine/InstCombiner.h"
+#include <bitset>
using namespace llvm;
using namespace PatternMatch;
@@ -2895,19 +2896,89 @@ Instruction *InstCombinerImpl::foldICmpSubConstant(ICmpInst &Cmp,
return new ICmpInst(SwappedPred, Add, ConstantInt::get(Ty, ~C));
}
+static Value *createLogicFromTable(const std::bitset<4> &Table, Value *Op0,
+ Value *Op1, IRBuilderBase &Builder,
+ bool HasOneUse) {
+ switch (Table.to_ulong()) {
+ case 0: // 0 0 0 0
+ return Builder.getFalse();
+ case 1: // 0 0 0 1
+ return HasOneUse ? Builder.CreateNot(Builder.CreateOr(Op0, Op1)) : nullptr;
+ case 2: // 0 0 1 0
+ return HasOneUse ? Builder.CreateAnd(Builder.CreateNot(Op0), Op1) : nullptr;
+ case 3: // 0 0 1 1
+ return Builder.CreateNot(Op0);
+ case 4: // 0 1 0 0
+ return HasOneUse ? Builder.CreateAnd(Op0, Builder.CreateNot(Op1)) : nullptr;
+ case 5: // 0 1 0 1
+ return Builder.CreateNot(Op1);
+ case 6: // 0 1 1 0
+ return Builder.CreateXor(Op0, Op1);
+ case 7: // 0 1 1 1
+ return HasOneUse ? Builder.CreateNot(Builder.CreateAnd(Op0, Op1)) : nullptr;
+ case 8: // 1 0 0 0
+ return Builder.CreateAnd(Op0, Op1);
+ case 9: // 1 0 0 1
+ return HasOneUse ? Builder.CreateNot(Builder.CreateXor(Op0, Op1)) : nullptr;
+ case 10: // 1 0 1 0
+ return Op1;
+ case 11: // 1 0 1 1
+ return HasOneUse ? Builder.CreateOr(Builder.CreateNot(Op0), Op1) : nullptr;
+ case 12: // 1 1 0 0
+ return Op0;
+ case 13: // 1 1 0 1
+ return HasOneUse ? Builder.CreateOr(Op0, Builder.CreateNot(Op1)) : nullptr;
+ case 14: // 1 1 1 0
+ return Builder.CreateOr(Op0, Op1);
+ case 15: // 1 1 1 1
+ return Builder.getTrue();
+ default:
+ llvm_unreachable("Invalid Operation");
+ }
+ return nullptr;
+}
+
/// Fold icmp (add X, Y), C.
Instruction *InstCombinerImpl::foldICmpAddConstant(ICmpInst &Cmp,
BinaryOperator *Add,
const APInt &C) {
Value *Y = Add->getOperand(1);
+ Value *X = Add->getOperand(0);
+
+ Value *Op0, *Op1;
+ Instruction *Ext0, *Ext1;
+ const CmpInst::Predicate Pred = Cmp.getPredicate();
+ if (match(Add,
+ m_Add(m_CombineAnd(m_Instruction(Ext0), m_ZExtOrSExt(m_Value(Op0))),
+ m_CombineAnd(m_Instruction(Ext1),
+ m_ZExtOrSExt(m_Value(Op1))))) &&
+ Op0->getType()->isIntOrIntVectorTy(1) &&
+ Op1->getType()->isIntOrIntVectorTy(1)) {
+ unsigned BW = C.getBitWidth();
+ std::bitset<4> Table;
+ auto ComputeTable = [&](bool Op0Val, bool Op1Val) {
+ int Res = 0;
+ if (Op0Val)
+ Res += isa<ZExtInst>(Ext0) ? 1 : -1;
+ if (Op1Val)
+ Res += isa<ZExtInst>(Ext1) ? 1 : -1;
+ return ICmpInst::compare(APInt(BW, Res, true), C, Pred);
+ };
+
+ Table[0] = ComputeTable(false, false);
+ Table[1] = ComputeTable(false, true);
+ Table[2] = ComputeTable(true, false);
+ Table[3] = ComputeTable(true, true);
+ if (auto *Cond =
+ createLogicFromTable(Table, Op0, Op1, Builder, Add->hasOneUse()))
+ return replaceInstUsesWith(Cmp, Cond);
+ }
const APInt *C2;
if (Cmp.isEquality() || !match(Y, m_APInt(C2)))
return nullptr;
// Fold icmp pred (add X, C2), C.
- Value *X = Add->getOperand(0);
Type *Ty = Add->getType();
- const CmpInst::Predicate Pred = Cmp.getPredicate();
// If the add does not wrap, we can always adjust the compare by subtracting
// the constants. Equality comparisons are handled elsewhere. SGE/SLE/UGE/ULE
@@ -6410,60 +6481,6 @@ Instruction *InstCombinerImpl::foldICmpUsingBoolRange(ICmpInst &I) {
Y->getType()->isIntOrIntVectorTy(1) && Pred == ICmpInst::ICMP_ULE)
return BinaryOperator::CreateOr(Builder.CreateIsNull(X), Y);
- const APInt *C;
- if (match(I.getOperand(0), m_c_Add(m_ZExt(m_Value(X)), m_SExt(m_Value(Y)))) &&
- match(I.getOperand(1), m_APInt(C)) &&
- X->getType()->isIntOrIntVectorTy(1) &&
- Y->getType()->isIntOrIntVectorTy(1)) {
- unsigned BitWidth = C->getBitWidth();
- Pred = I.getPredicate();
- APInt Zero = APInt::getZero(BitWidth);
- APInt MinusOne = APInt::getAllOnes(BitWidth);
- APInt One(BitWidth, 1);
- if ((C->sgt(Zero) && Pred == ICmpInst::ICMP_SGT) ||
- (C->slt(Zero) && Pred == ICmpInst::ICMP_SLT))
- return replaceInstUsesWith(I, ConstantInt::getFalse(I.getType()));
- if ((C->sgt(One) && Pred == ICmpInst::ICMP_SLT) ||
- (C->slt(MinusOne) && Pred == ICmpInst::ICMP_SGT))
- return replaceInstUsesWith(I, ConstantInt::getTrue(I.getType()));
-
- if (I.getOperand(0)->hasOneUse()) {
- APInt NewC = *C;
- // canonicalize predicate to eq/ne
- if ((*C == Zero && Pred == ICmpInst::ICMP_SLT) ||
- (*C != Zero && *C != MinusOne && Pred == ICmpInst::ICMP_UGT)) {
- // x s< 0 in [-1, 1] --> x == -1
- // x u> 1(or any const !=0 !=-1) in [-1, 1] --> x == -1
- NewC = MinusOne;
- Pred = ICmpInst::ICMP_EQ;
- } else if ((*C == MinusOne && Pred == ICmpInst::ICMP_SGT) ||
- (*C != Zero && *C != One && Pred == ICmpInst::ICMP_ULT)) {
- // x s> -1 in [-1, 1] --> x != -1
- // x u< -1 in [-1, 1] --> x != -1
- Pred = ICmpInst::ICMP_NE;
- } else if (*C == Zero && Pred == ICmpInst::ICMP_SGT) {
- // x s> 0 in [-1, 1] --> x == 1
- NewC = One;
- Pred = ICmpInst::ICMP_EQ;
- } else if (*C == One && Pred == ICmpInst::ICMP_SLT) {
- // x s< 1 in [-1, 1] --> x != 1
- Pred = ICmpInst::ICMP_NE;
- }
-
- if (NewC == MinusOne) {
- if (Pred == ICmpInst::ICMP_EQ)
- return BinaryOperator::CreateAnd(Builder.CreateNot(X), Y);
- if (Pred == ICmpInst::ICMP_NE)
- return BinaryOperator::CreateOr(X, Builder.CreateNot(Y));
- } else if (NewC == One) {
- if (Pred == ICmpInst::ICMP_EQ)
- return BinaryOperator::CreateAnd(X, Builder.CreateNot(Y));
- if (Pred == ICmpInst::ICMP_NE)
- return BinaryOperator::CreateOr(Builder.CreateNot(X), Y);
- }
- }
- }
-
return nullptr;
}
diff --git a/llvm/test/Transforms/InstCombine/icmp-add.ll b/llvm/test/Transforms/InstCombine/icmp-add.ll
index 8a4b4e7448bf8a4..3a3c1b8b65e7ea0 100644
--- a/llvm/test/Transforms/InstCombine/icmp-add.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-add.ll
@@ -86,10 +86,7 @@ bb:
define i1 @cvt_icmp_1_zext_plus_zext_eq(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_1_zext_plus_zext_eq(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp eq i32 [[I3]], 1
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[ARG1:%.*]], [[ARG:%.*]]
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -103,10 +100,7 @@ bb:
define i1 @cvt_icmp_2_zext_plus_zext_eq(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_2_zext_plus_zext_eq(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], 2
+; CHECK-NEXT: [[T:%.*]] = and i1 [[ARG:%.*]], [[ARG1:%.*]]
; CHECK-NEXT: ret i1 [[T]]
;
bb:
@@ -120,10 +114,7 @@ bb:
define i1 @cvt_icmp_neg_2_sext_plus_sext_eq(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_neg_2_sext_plus_sext_eq(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], -2
+; CHECK-NEXT: [[T:%.*]] = and i1 [[ARG:%.*]], [[ARG1:%.*]]
; CHECK-NEXT: ret i1 [[T]]
;
bb:
@@ -137,10 +128,7 @@ bb:
define i1 @cvt_icmp_neg_1_sext_plus_sext_eq(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_neg_1_sext_plus_sext_eq(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], -1
+; CHECK-NEXT: [[T:%.*]] = xor i1 [[ARG:%.*]], [[ARG1:%.*]]
; CHECK-NEXT: ret i1 [[T]]
;
bb:
@@ -169,11 +157,7 @@ bb:
define i1 @cvt_icmp_1_sext_plus_sext_eq(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_1_sext_plus_sext_eq(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], 1
-; CHECK-NEXT: ret i1 [[T]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = sext i1 %arg to i32
@@ -186,11 +170,7 @@ bb:
define i1 @cvt_icmp_2_sext_plus_sext_eq(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_2_sext_plus_sext_eq(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], 2
-; CHECK-NEXT: ret i1 [[T]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = sext i1 %arg to i32
@@ -203,11 +183,7 @@ bb:
define i1 @cvt_icmp_neg_2_sext_plus_zext_eq(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_neg_2_sext_plus_zext_eq(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], -2
-; CHECK-NEXT: ret i1 [[T]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = sext i1 %arg to i32
@@ -265,11 +241,7 @@ bb:
define i1 @cvt_icmp_2_sext_plus_zext_eq(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_2_sext_plus_zext_eq(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], 2
-; CHECK-NEXT: ret i1 [[T]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = sext i1 %arg to i32
@@ -308,8 +280,8 @@ bb:
define i1 @cvt_icmp_0_zext_plus_zext_ne(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_0_zext_plus_zext_ne(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
-; CHECK-NEXT: ret i1 [[TMP0]]
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
;
bb:
%i = zext i1 %arg to i32
@@ -322,10 +294,8 @@ bb:
define i1 @cvt_icmp_1_zext_plus_zext_ne(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_1_zext_plus_zext_ne(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp ne i32 [[I3]], 1
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -339,10 +309,8 @@ bb:
define i1 @cvt_icmp_2_zext_plus_zext_ne(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_2_zext_plus_zext_ne(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], 2
+; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT: [[T:%.*]] = xor i1 [[TMP0]], true
; CHECK-NEXT: ret i1 [[T]]
;
bb:
@@ -356,10 +324,8 @@ bb:
define i1 @cvt_icmp_neg_2_sext_plus_sext_ne(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_neg_2_sext_plus_sext_ne(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], -2
+; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT: [[T:%.*]] = xor i1 [[TMP0]], true
; CHECK-NEXT: ret i1 [[T]]
;
bb:
@@ -373,10 +339,8 @@ bb:
define i1 @cvt_icmp_neg_1_sext_plus_sext_ne(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_neg_1_sext_plus_sext_ne(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], -1
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT: [[T:%.*]] = xor i1 [[TMP0]], true
; CHECK-NEXT: ret i1 [[T]]
;
bb:
@@ -390,8 +354,8 @@ bb:
define i1 @cvt_icmp_0_sext_plus_sext_ne(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_0_sext_plus_sext_ne(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG:%.*]], [[ARG1:%.*]]
-; CHECK-NEXT: ret i1 [[TMP0]]
+; CHECK-NEXT: [[T:%.*]] = or i1 [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[T]]
;
bb:
%i = sext i1 %arg to i32
@@ -404,11 +368,7 @@ bb:
define i1 @cvt_icmp_1_sext_plus_sext_ne(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_1_sext_plus_sext_ne(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], 1
-; CHECK-NEXT: ret i1 [[T]]
+; CHECK-NEXT: ret i1 true
;
bb:
%i = sext i1 %arg to i32
@@ -421,11 +381,7 @@ bb:
define i1 @cvt_icmp_2_sext_plus_sext_ne(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_2_sext_plus_sext_ne(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], 2
-; CHECK-NEXT: ret i1 [[T]]
+; CHECK-NEXT: ret i1 true
;
bb:
%i = sext i1 %arg to i32
@@ -438,11 +394,7 @@ bb:
define i1 @cvt_icmp_neg_2_sext_plus_zext_ne(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_neg_2_sext_plus_zext_ne(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], -2
-; CHECK-NEXT: ret i1 [[T]]
+; CHECK-NEXT: ret i1 true
;
bb:
%i = sext i1 %arg to i32
@@ -499,11 +451,7 @@ bb:
define i1 @cvt_icmp_2_sext_plus_zext_ne(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_2_sext_plus_zext_ne(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], 2
-; CHECK-NEXT: ret i1 [[T]]
+; CHECK-NEXT: ret i1 true
;
bb:
%i = sext i1 %arg to i32
@@ -519,11 +467,7 @@ bb:
define i1 @cvt_icmp_neg_2_zext_plus_sext_eq(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_neg_2_zext_plus_sext_eq(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], -2
-; CHECK-NEXT: ret i1 [[T]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = zext i1 %arg to i32
@@ -581,11 +525,7 @@ bb:
define i1 @cvt_icmp_2_zext_plus_sext_eq(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_2_zext_plus_sext_eq(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I3]], 2
-; CHECK-NEXT: ret i1 [[T]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = zext i1 %arg to i32
@@ -598,11 +538,7 @@ bb:
define i1 @cvt_icmp_neg_2_zext_plus_sext_ne(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_neg_2_zext_plus_sext_ne(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], -2
-; CHECK-NEXT: ret i1 [[T]]
+; CHECK-NEXT: ret i1 true
;
bb:
%i = zext i1 %arg to i32
@@ -659,11 +595,7 @@ bb:
define i1 @cvt_icmp_2_zext_plus_sext_ne(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @cvt_icmp_2_zext_plus_sext_ne(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I]], [[I2]]
-; CHECK-NEXT: [[T:%.*]] = icmp ne i32 [[I3]], 2
-; CHECK-NEXT: ret i1 [[T]]
+; CHECK-NEXT: ret i1 true
;
bb:
%i = zext i1 %arg to i32
@@ -678,12 +610,9 @@ bb:
define i1 @test_cvt_icmp1(i1 %arg, i1 %arg1, ptr %p) {
; CHECK-LABEL: @test_cvt_icmp1(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG]] to i32
+; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG:%.*]] to i32
; CHECK-NEXT: store i32 [[I2]], ptr [[P:%.*]], align 4
-; CHECK-NEXT: [[I4:%.*]] = add nuw nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[I4]], 1
-; CHECK-NEXT: ret i1 [[T]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = zext i1 %arg to i32
@@ -755,10 +684,8 @@ bb:
define i1 @test_zext_zext_cvt_2_ult_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_zext_cvt_2_ult_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp ult i32 [[I3]], 2
+; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -787,10 +714,8 @@ bb:
define i1 @test_sext_sext_cvt_neg_1_ult_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_neg_1_ult_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp ne i32 [[I3]], -1
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -949,8 +874,8 @@ bb:
define i1 @test_cvt_icmp4(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp4(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
-; CHECK-NEXT: ret i1 [[TMP0]]
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
;
bb:
%i = zext i1 %arg to i32
@@ -976,10 +901,7 @@ bb:
define i1 @test_zext_zext_cvt_1_ugt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_zext_cvt_1_ugt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp ugt i32 [[I3]], 1
+; CHECK-NEXT: [[I4:%.*]] = and i1 [[ARG1:%.*]], [[ARG:%.*]]
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -993,11 +915,7 @@ bb:
define i1 @test_zext_zext_cvt_2_ugt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_zext_cvt_2_ugt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp eq i32 [[I3]], 3
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = zext i1 %arg to i32
@@ -1010,10 +928,7 @@ bb:
define i1 @test_sext_sext_cvt_neg_2_ugt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_neg_2_ugt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp eq i32 [[I3]], -1
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[ARG1:%.*]], [[ARG:%.*]]
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -1027,8 +942,8 @@ bb:
define i1 @test_sext_sext_cvt_0_ugt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_0_ugt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
-; CHECK-NEXT: ret i1 [[TMP0]]
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
;
bb:
%i = sext i1 %arg to i32
@@ -1041,10 +956,7 @@ bb:
define i1 @test_sext_sext_cvt_2_ugt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_2_ugt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp ugt i32 [[I3]], 2
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -1101,8 +1013,8 @@ define i1 @test_zext_sext_cvt_1_ugt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_sext_cvt_1_ugt_icmp(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
-; CHECK-NEXT: [[I4:%.*]] = and i1 [[TMP0]], [[ARG1:%.*]]
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: [[TMP1:%.*]] = and i1 [[TMP0]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
;
bb:
%i = zext i1 %arg to i32
@@ -1130,8 +1042,8 @@ bb:
define i1 @test_cvt_icmp5(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp5(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
-; CHECK-NEXT: ret i1 [[TMP0]]
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
;
bb:
%i = zext i1 %arg to i32
@@ -1144,10 +1056,8 @@ bb:
define i1 @test_cvt_icmp6(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp6(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp ult i32 [[I3]], 2
+; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -1162,10 +1072,7 @@ bb:
define i1 @test_cvt_icmp7(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp7(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp ugt i32 [[I3]], 1
+; CHECK-NEXT: [[I4:%.*]] = and i1 [[ARG1:%.*]], [[ARG:%.*]]
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -1205,11 +1112,7 @@ bb:
define i1 @test_zext_zext_cvt_2_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_zext_cvt_2_sgt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp eq i32 [[I3]], 3
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = zext i1 %arg to i32
@@ -1222,10 +1125,8 @@ bb:
define i1 @test_sext_sext_cvt_neg_2_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_neg_2_sgt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 [[I3]], -2
+; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -1239,11 +1140,7 @@ bb:
define i1 @test_sext_sext_cvt_0_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_0_sgt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 [[I3]], 0
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = sext i1 %arg to i32
@@ -1256,11 +1153,7 @@ bb:
define i1 @test_sext_sext_cvt_2_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_2_sgt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 [[I3]], 2
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = sext i1 %arg to i32
@@ -1286,8 +1179,8 @@ bb:
define i1 @test_zext_sext_cvt_neg_1_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_sext_cvt_neg_1_sgt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], true
-; CHECK-NEXT: [[I4:%.*]] = or i1 [[TMP0]], [[ARG:%.*]]
+; CHECK-NEXT: [[ARG1_NOT:%.*]] = xor i1 [[ARG1:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG1_NOT]], [[ARG:%.*]]
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -1369,10 +1262,8 @@ bb:
define i1 @test_zext_zext_cvt_2_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_zext_cvt_2_slt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp ult i32 [[I3]], 2
+; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -1386,11 +1277,7 @@ bb:
define i1 @test_sext_sext_cvt_neg_2_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_neg_2_slt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp slt i32 [[I3]], -2
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = sext i1 %arg to i32
@@ -1417,11 +1304,7 @@ bb:
define i1 @test_sext_sext_cvt_2_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_2_slt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp slt i32 [[I3]], 2
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: ret i1 true
;
bb:
%i = sext i1 %arg to i32
@@ -1461,8 +1344,8 @@ define i1 @test_zext_sext_cvt_0_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_sext_cvt_0_slt_icmp(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
-; CHECK-NEXT: [[I4:%.*]] = and i1 [[TMP0]], [[ARG1:%.*]]
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: [[TMP1:%.*]] = and i1 [[TMP0]], [[ARG1:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
;
bb:
%i = zext i1 %arg to i32
@@ -1503,8 +1386,8 @@ bb:
define i1 @test_cvt_icmp8(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp8(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
-; CHECK-NEXT: ret i1 [[TMP0]]
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
;
bb:
%i = zext i1 %arg to i32
@@ -1532,10 +1415,8 @@ bb:
define i1 @test_cvt_icmp10(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp10(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = zext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nuw nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp ult i32 [[I3]], 2
+; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -1549,10 +1430,7 @@ bb:
define i1 @test_cvt_icmp11(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp11(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp ugt i32 [[I3]], 2
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -1566,8 +1444,8 @@ bb:
define i1 @test_cvt_icmp12(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp12(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
-; CHECK-NEXT: ret i1 [[TMP0]]
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
;
bb:
%i = sext i1 %arg to i32
@@ -1595,10 +1473,8 @@ bb:
define i1 @test_cvt_icmp14(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp14(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp ult i32 [[I3]], 3
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -1612,11 +1488,7 @@ bb:
define i1 @test_cvt_icmp15(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp15(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 [[I3]], 2
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = sext i1 %arg to i32
@@ -1629,11 +1501,7 @@ bb:
define i1 @test_cvt_icmp16(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp16(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 [[I3]], 1
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = sext i1 %arg to i32
@@ -1646,11 +1514,7 @@ bb:
define i1 @test_cvt_icmp17(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp17(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp slt i32 [[I3]], 2
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: ret i1 true
;
bb:
%i = sext i1 %arg to i32
@@ -1663,11 +1527,7 @@ bb:
define i1 @test_cvt_icmp18(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp18(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = sext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp slt i32 [[I3]], 3
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: ret i1 true
;
bb:
%i = sext i1 %arg to i32
@@ -1724,10 +1584,8 @@ bb:
define i1 @test_cvt_icmp22(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp22(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = sext i1 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[I2:%.*]] = zext i1 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[I3:%.*]] = add nsw i32 [[I2]], [[I]]
-; CHECK-NEXT: [[I4:%.*]] = icmp ult i32 [[I3]], 3
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[TMP0]], [[ARG1:%.*]]
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -1754,8 +1612,8 @@ bb:
define i1 @test_cvt_icmp24(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp24(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
-; CHECK-NEXT: [[I4:%.*]] = or i1 [[TMP0]], [[ARG1:%.*]]
+; CHECK-NEXT: [[ARG_NOT:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG_NOT]], [[ARG1:%.*]]
; CHECK-NEXT: ret i1 [[I4]]
;
bb:
@@ -1770,8 +1628,8 @@ define i1 @test_cvt_icmp25(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp25(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], true
-; CHECK-NEXT: [[I4:%.*]] = and i1 [[TMP0]], [[ARG:%.*]]
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: [[TMP1:%.*]] = and i1 [[TMP0]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
;
bb:
%i = sext i1 %arg to i32
diff --git a/llvm/test/Transforms/InstCombine/icmp-range.ll b/llvm/test/Transforms/InstCombine/icmp-range.ll
index a6b629373946e30..7e8db7767c199cb 100644
--- a/llvm/test/Transforms/InstCombine/icmp-range.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-range.ll
@@ -729,8 +729,8 @@ define i1 @zext_sext_add_icmp_ne_minus1(i1 %a, i1 %b) {
define i1 @zext_sext_add_icmp_sgt_minus1(i1 %a, i1 %b) {
; CHECK-LABEL: @zext_sext_add_icmp_sgt_minus1(
-; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[B:%.*]], true
-; CHECK-NEXT: [[R:%.*]] = or i1 [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[B_NOT:%.*]] = xor i1 [[B:%.*]], true
+; CHECK-NEXT: [[R:%.*]] = or i1 [[B_NOT]], [[A:%.*]]
; CHECK-NEXT: ret i1 [[R]]
;
%zext.a = zext i1 %a to i8
@@ -775,8 +775,8 @@ define i1 @zext_sext_add_icmp_sgt_0(i1 %a, i1 %b) {
define i1 @zext_sext_add_icmp_slt_0(i1 %a, i1 %b) {
; CHECK-LABEL: @zext_sext_add_icmp_slt_0(
; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[A:%.*]], true
-; CHECK-NEXT: [[R:%.*]] = and i1 [[TMP1]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[R]]
+; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[TMP1]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP2]]
;
%zext.a = zext i1 %a to i8
%sext.b = sext i1 %b to i8
@@ -835,8 +835,8 @@ define i1 @zext_sext_add_icmp_slt_1(i1 %a, i1 %b) {
define i1 @zext_sext_add_icmp_ugt_1(i1 %a, i1 %b) {
; CHECK-LABEL: @zext_sext_add_icmp_ugt_1(
; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[A:%.*]], true
-; CHECK-NEXT: [[R:%.*]] = and i1 [[TMP1]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[R]]
+; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[TMP1]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP2]]
;
%zext.a = zext i1 %a to i8
%sext.b = sext i1 %b to i8
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